Description: Verilog HDL: Magnitude
For a vector (a,b), the magnitude representation is the following:
A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
-Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix Platform: |
Size: 12288 |
Author:郝晋 |
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Description: cordic methods describe essentially the same algorithm that with suitably chosen inputs can be used to calculate a whole range of scientific functions including sin, cos, tan, arctan, arcsin, arccos, sinh, cosh, tanh, arctanh, log, exp, square root and even multiply and divide.
the method dates back to volder [1959], and due to its versatility and compactness, it made possible the microcoding of the hp35 pocket scientific calculator in 1972.
here is some code to illustrate the techniques. ive split the methods into three parts linear, circular and hyperbolic. in the hp35 microcode these would be unified into one function (for space reasons). because the linear mode can perform multiply and divide, you only need add/subtract and shift to complete the implementation.
you can select in the code whether to do the multiples and divides also by cordic means. other multiplies and divides are all powers of 2 (these dont count). to eliminate these too, would involve ieee hackery.-cordic methods describe essentially the same algorithm that with suitably chosen inputs can be used to calculate a whole range of scientific functions including sin, cos, tan, arctan, arcsin, arccos, sinh, cosh, tanh, arctanh, log, exp, square root and even multiply and divide.
the method dates back to volder [1959], and due to its versatility and compactness, it made possible the microcoding of the hp35 pocket scientific calculator in 1972.
here is some code to illustrate the techniques. ive split the methods into three parts linear, circular and hyperbolic. in the hp35 microcode these would be unified into one function (for space reasons). because the linear mode can perform multiply and divide, you only need add/subtract and shift to complete the implementation.
you can select in the code whether to do the multiples and divides also by cordic means. other multiplies and divides are all powers of 2 (these dont count). to eliminate these too, would involve ieee hackery.
Platform: |
Size: 2048 |
Author:waqas |
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Description: ABSTRACT:
Low power consumption and smaller area are some of the most important criteria for the
fabrication of DSP systems and high performance systems. Optimizing the speed and
area of the multiplier is a major design issue. However, area and speed are usually
conflicting constraints so that improving speed results mostly in larger areas. In our
project we try to determine the best solution to this problem by comparing a few
multipliers.
This project presents an efficient implementation of high speed multiplier using the shift
and add method, Radix_2, Radix_4 modified Booth multiplier algorithm. In this project
we compare the working of the three multiplier by implementing each of them separately
in FIR filter. Platform: |
Size: 379904 |
Author:phitoan |
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Description: Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers
etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm
(FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different
topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and
shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder,
carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective
is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative
study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on
the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis
of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is
used to implement the proposed designs in VHDL. Platform: |
Size: 1123027 |
Author:nalevihtkas |
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Search - shift-and-add algorithm in vhdl