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[VHDL-FPGA-Verilog] cordic DL : 0: 用于实现sin，cos三角函数计数的VHDL程序代码-towards sin, cos trigonometry count VHDL code
Update : 2025-02-17 Size : 2kb Publisher : 王森
[Algorithm] SINDDS DL : 0: sin数据生成，可以生成DDS的ROM文件-sin data generation, the generation DDS ROM documents
Update : 2025-02-17 Size : 183kb Publisher : lxq
[Other] sin DL : 0: Quartus II设计正弦信号发生器。本节通过正弦信号发生器的设计对QuartusII的一些重要功能作一些说明。对本节的详细了解有利于对以后章节有关DSP Builder的应用和设计有更好的理解。-Quartus II design sinusoidal signal generator. This section through the sinusoidal signal generator QuartusII the design of some of the important features to make some notes. Of this section to learn more about the future in favor of the relevant sections of the application of DSP Builder and design have a better understanding.
Update : 2025-02-17 Size : 849kb Publisher : yehui
[VHDL-FPGA-Verilog] sin DL : 0: sin產生器，可以於VHDL產生sin之數值波形，進而輸出至dac做轉換-sin generator can produce sin in VHDL of the numerical waveform, and then make the conversion output to dac
Update : 2025-02-17 Size : 1.03mb Publisher : lin
[VHDL-FPGA-Verilog] VHDL-XILINX-EXAMPLE26 DL : 0: [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现ADC0809的采样电路设计][15--DMA方式A/D采样控制电路设计][16--硬件电子琴][17--乐曲自动演奏][18--秒表][19--移位相加8位硬件乘法器][20--VGA图像显示控制器(彩条)][21--VGA图像显示控制器][22--等精度频率计][23--模拟波形发生器][24--模拟示波器][25--通用异步收发器(UART)][26--8位CPU设计(COP2000)]
Update : 2025-02-17 Size : 3.52mb Publisher : hawd
[VHDL-FPGA-Verilog] Sin_wave DL : 0: sin波形信号发生起的程序 VHDL语言描述 QUartus-sin waveform signal from the procedure described in VHDL language Quartus
Update : 2025-02-17 Size : 472kb Publisher : luyingc
[VHDL-FPGA-Verilog] sin DL : 0: 基于Quartus II 5.0编写的正弦波发生器，可控频率，用vhdl编写的-Quartus II 5.0 on the preparation of the sine wave generator, controllable frequency, prepared using VHDL
Update : 2025-02-17 Size : 464kb Publisher : uuk
[VHDL-FPGA-Verilog] sin DL : 0: 正弦信号发生器程序,用VERILOG写出。-Sinusoidal signal generator procedures, used to write Verilog.
Update : 2025-02-17 Size : 2.41mb Publisher : 112254
[VHDL-FPGA-Verilog] sin DL : 0: 基于fpga的正弦波发生器设计，有一定的参考价值，写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
Update : 2025-02-17 Size : 618kb Publisher : qlg
[VHDL-FPGA-Verilog] SIN DL : 0: 使用VHDL语言和CPLD芯片生成39KHz的信号-The use of VHDL language and CPLD chip 39KHz signal generated
Update : 2025-02-17 Size : 214kb Publisher : Beyond
[VHDL-FPGA-Verilog] sin.tar DL : 0: 神奇的sin波生成verilog源码，非常简单的代码无需乘法即可生成sin,cos，值得搞算法的人借鉴-Magic sin wave generated Verilog source code, the code is very simple multiplication can be generated without sin, cos, worthy people from engaging in algorithm
Update : 2025-02-17 Size : 2kb Publisher : yangyu
[Algorithm] cordic DL : 0: cordic methods describe essentially the same algorithm that with suitably chosen inputs can be used to calculate a whole range of scientific functions including sin, cos, tan, arctan, arcsin, arccos, sinh, cosh, tanh, arctanh, log, exp, square root and even multiply and divide. the method dates back to volder [1959], and due to its versatility and compactness, it made possible the microcoding of the hp35 pocket scientific calculator in 1972. here is some code to illustrate the techniques. ive split the methods into three parts linear, circular and hyperbolic. in the hp35 microcode these would be unified into one function (for space reasons). because the linear mode can perform multiply and divide, you only need add/subtract and shift to complete the implementation. you can select in the code whether to do the multiples and divides also by cordic means. other multiplies and divides are all powers of 2 (these dont count). to eliminate these too, would involve ieee hackery.-cordic methods describe essentially the same algorithm that with suitably chosen inputs can be used to calculate a whole range of scientific functions including sin, cos, tan, arctan, arcsin, arccos, sinh, cosh, tanh, arctanh, log, exp, square root and even multiply and divide. the method dates back to volder [1959], and due to its versatility and compactness, it made possible the microcoding of the hp35 pocket scientific calculator in 1972. here is some code to illustrate the techniques. ive split the methods into three parts linear, circular and hyperbolic. in the hp35 microcode these would be unified into one function (for space reasons). because the linear mode can perform multiply and divide, you only need add/subtract and shift to complete the implementation. you can select in the code whether to do the multiples and divides also by cordic means. other multiplies and divides are all powers of 2 (these dont count). to eliminate these too, would involve ieee hackery.
Update : 2025-02-17 Size : 2kb Publisher : waqas
[VHDL-FPGA-Verilog] sin DL : 0: 用Verilog语言在FPGA内实现一256个采样点的正弦波，已尝试，挺好用的-Verilog language used in the FPGA to achieve one of the 256 sampling points sine wave, I have already tried it, very useful~ ~ ~
Update : 2025-02-17 Size : 102kb Publisher :
[VHDL-FPGA-Verilog] CordicNCO DL : 0: 基于CORDIC算法的，数字控制振荡器的设计。带测试程序，输入一个振荡频率，输出SIN和COS的波形！-Based on the CORDIC algorithm, the digital controlled oscillator design. With test procedures, enter a oscillation frequency, the output waveform SIN and COS!
Update : 2025-02-17 Size : 4kb Publisher : 咚咚
[VHDL-FPGA-Verilog] sin DL : 0: 用VHDL编写的实现EDA实验中显示sin波形代码。简单易懂，应该对大家都有帮助-VHDL prepared with the realization of the experiment showed that EDA code sin waveform. Easy-to-read, should help to everyone
Update : 2025-02-17 Size : 1kb Publisher : 林怡
[DSP program] sin_cos DL : 0: Sin & Cos generator (one from DSP steps)
Update : 2025-02-17 Size : 38kb Publisher : jools
[VHDL-FPGA-Verilog] dds-sin-generator DL : 0: 正铉波发生器 dds 一共有8个vhdl文件组成。其中dds为头文件-dds
Update : 2025-02-17 Size : 7kb Publisher : 李磊
[VHDL-FPGA-Verilog] VHDL(sin) DL : 0: 基于ROM的正弦波发生器的设计一．实验目的 1. 学习VHDL的综合设计应用 2. 学习基于ROM的正弦波发生器的设计二．实验内容设计基于ROM的正弦波发生器，对其编译，仿真。具体要求： 1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based sine wave generator design 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning ROM-based sine wave generator design 2. Experimental content ROM-based sine wave generator design, its compilation, simulation. Specific requirements: 1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB. 3. The 50MHz input clock.
Update : 2025-02-17 Size : 17kb Publisher : 爱好
[assembly language] sin DL : 0: sin正弦波的产生 DDS FPGA VHDL语言-sin sine wave generation DDS FPGA VHDL language
Update : 2025-02-17 Size : 1.65mb Publisher : 王盛力
[VHDL-FPGA-Verilog] sin DL : 0: QUARTUSS||环境下的简易正弦信号发生器的设计，VERILOG 代码，用到了嵌入式逻辑分析仪-QUARTUSS | | environment simple sinusoidal signal generator, VERILOG code, use the embedded logic analyzer
Update : 2025-02-17 Size : 2.82mb Publisher : sujiebin

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