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[VHDL-FPGA-Verilog] 一个波形发生器和sine波形发生器

Description: 这是一个典型的正玄波发生器程序和一个任意波形发生器程序，大家可以参考学习，对于vhdl入门还是很有帮助的-This is a typical wave generator Shogen procedures and an arbitrary waveform generator procedures, Members can take a learning portal for VHDL or helpful
Platform: | Size: 3072 | Author: 张云鹏 | Hits:

[Crack Hack] keygen

Description: ADI VISUALDSP 4.0 序列号发生器-ADI VISUALDSP 4.0 serial number generator
Platform: | Size: 267264 | Author: 李志 | Hits:

[assembly language] sine

Description: 用verilog语言编的正弦波发生器，可以用QuartusII来打开这个源码，也可以转换成VHDL语言-Verilog language prepared by the sine wave generator can be used QuartusII to open the source code can also be converted into VHDL language
Platform: | Size: 104448 | Author: 雨孩 | Hits:

[MiddleWare] pwm_DAC

Description: 使用msp430的定时器生成PWM波通过硬件滤波器实现DAC功能，一阶滤波为直流电平，二阶可以生成任意波形，如正弦波，锯齿波等-MSP430 timer used to generate PWM wave through the hardware filter DAC functions, first-order filter for the DC-ping, the second order can generate arbitrary waveform, such as sine wave, sawtooth wave, etc.
Platform: | Size: 17408 | Author: 贺虎 | Hits:

[Other] signal-generator

Description: 这是一个信号发生器的labview源程序，模拟正弦波、三角波、方波等五种波形输出，频率、幅值、相位可调。 -This is a signal generator of the LabVIEW source code, analog sine wave, triangle wave, square wave output waveform five, frequency, amplitude, phase adjustable.
Platform: | Size: 10240 | Author: pf6601 | Hits:

[SCM] wave-generator

Description: 产生方波，三角波，正弦波，余弦波等波形，并且可以自由选择和切换，最后可以用于波形输出-Have a square wave, triangle wave, sine wave, cosine wave, such as waveform, and can freely choose and switch, and finally can be used for waveform output
Platform: | Size: 6144 | Author: 周易 | Hits:

[VHDL-FPGA-Verilog] sin

Description: 基于fpga的正弦波发生器设计，有一定的参考价值，写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
Platform: | Size: 632832 | Author: qlg | Hits:

[VHDL-FPGA-Verilog] sine-generator

Description: 原创：采用VHDL语言编写的正弦信号发生器。rom采用quartus自带的lpm生成，可产生正弦波。更改rom内容可改变波形-Original: Using VHDL languages sinusoidal signal generator. rom using Quartus LPM s own generation, can produce sine wave. Rom content changes can change the waveform
Platform: | Size: 675840 | Author: zzwuyu | Hits:

[VHDL-FPGA-Verilog] VHDL-ROM4

Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

[VHDL-FPGA-Verilog] sine_testbench

Description: Sine generator in VHDL.
Platform: | Size: 5120 | Author: Mike | Hits:

[Other] Sine

Description: 正弦波发生器，可以让大家学习正弦多种产生方法，可以设计具体电路-Sine wave generator, allowing them to learn the method for multiple sinusoidal, can design a specific circuit
Platform: | Size: 1028096 | Author: 秦寅 | Hits:

[SCM] Sine

Description: 标准正弦信号发生器,并且含有正弦表,对于新手有些帮助-Standard sinusoidal signal generator, and contain sinusoidal form, and some help for novice
Platform: | Size: 2530304 | Author: 张金斗 | Hits:

[SCM] generator

Description: 正弦波(三角波）发生器程序，可产生三角波，很实用-Sine wave (triangular wave) generator
Platform: | Size: 2048 | Author: 一泓 | Hits:

[Embeded-SCM Develop] Multi-waveform-generator

Description: 51单片机，C语言写的，可以产生锯齿波，三角波，方波，正弦波。该工程文件在keil环境下编译，用proteus仿真通过。-can produce triangle wave, square wave, sine wave. The project is compiled under keil environment, and pass proteus simulation.
Platform: | Size: 225280 | Author: jane | Hits:

[Communication] sine

Description: DPSK sine generator sample code
Platform: | Size: 231424 | Author: kcj | Hits:

[matlab] bd

Description: 正弦发生器，可以根据自己的需要改变参数，实现仿真-an example solution of sine wave generator
Platform: | Size: 4096 | Author: 晨宇 | Hits:

[VHDL-FPGA-Verilog] sine_vhdl

Description: this a snipet of code about the sine generator implementation in vhdl-this is a snipet of code about the sine generator implementation in vhdl
Platform: | Size: 1059840 | Author: boulou | Hits:

[SCM] Low-Frequency-SINE-Generator

Description: 一个简单的DDS实现正弦波输出的试验，内附PROTEUS 仿真程序。本例只实现了正弦波功能。-DDS to achieve a simple sine wave output test.
Platform: | Size: 50176 | Author: dali9165 | Hits:

[VHDL-FPGA-Verilog] sine-generator

Description: ROM型正弦信号发生器，从rom中读取正弦波的点，循环输出，经AD生成波形，环境为quartus-sine generator in quartus
Platform: | Size: 677888 | Author: 张文 | Hits:

[VHDL-FPGA-Verilog] quartus2-Sine-generator

Description: quartus2设计正弦发生器 ,仿真出正弦波形-Sine generator design by quartus2
Platform: | Size: 876544 | Author: chen | Hits:
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