Description: Original: Using VHDL languages sinusoidal signal generator. rom using Quartus LPM s own generation, can produce sine wave. Rom content changes can change the waveform
- [yesignal] - signal generation : can generate all typ
- [sina] - Sinusoidal signal generator, data, proce
- [sin_gnt] - Application macros module- realize sinus
- [DDS] - DDS-based digital phase-shifting sinusoi
- [FIFO] - VERILOG written using FIFO procedures, c
- [VHDL-ROM4] - ROM-based design of the sine wave genera
- [sin] - Sinusoidal signal generator source file
- [EP1C3_12_10_PHAS] - FPGA-based phase-shifting of the DDS sig
- [vhdl_dds] - VHDL language using a simple DDS, easy t
- [shejibaogao] - Electronic design, including some import
File list (Check if you may need any files):
正弦信号发生器
..............\db
..............\..\altsyncram_4d51.tdf
..............\..\altsyncram_7sv.tdf
..............\..\altsyncram_b192.tdf
..............\..\decode_rpe.tdf
..............\..\sine.asm.qmsg
..............\..\sine.asm_labs.ddb
..............\..\sine.cbx.xml
..............\..\sine.cmp.cdb
..............\..\sine.cmp.hdb
..............\..\sine.cmp.logdb
..............\..\sine.cmp.qrpt
..............\..\sine.cmp.rdb
..............\..\sine.cmp.tdb
..............\..\sine.cmp0.ddb
..............\..\sine.cmp2.ddb
..............\..\sine.dbp
..............\..\sine.db_info
..............\..\sine.eco.cdb
..............\..\sine.eds_overflow
..............\..\sine.fit.qmsg
..............\..\sine.hier_info
..............\..\sine.hif
..............\..\sine.map.cdb
..............\..\sine.map.hdb
..............\..\sine.map.logdb
..............\..\sine.map.qmsg
..............\..\sine.pre_map.cdb
..............\..\sine.pre_map.hdb
..............\..\sine.psp
..............\..\sine.rpp.qmsg
..............\..\sine.rtlv.hdb
..............\..\sine.rtlv_sg.cdb
..............\..\sine.rtlv_sg_swap.cdb
..............\..\sine.sgate.rvd
..............\..\sine.sgate_sm.rvd
..............\..\sine.sgdiff.cdb
..............\..\sine.sgdiff.hdb
..............\..\sine.signalprobe.cdb
..............\..\sine.sim.hdb
..............\..\sine.sim.qmsg
..............\..\sine.sim.qrpt
..............\..\sine.sim.rdb
..............\..\sine.sim.vwf
..............\..\sine.sld_design_entry.sci
..............\..\sine.sld_design_entry_dsc.sci
..............\..\sine.syn_hier_info
..............\..\sine.tan.qmsg
..............\rom1.cmp
..............\rom1.vhd
..............\rom1.vwf
..............\rom1_inst.vhd
..............\SDATA.HEX
..............\sine.asm.rpt
..............\sine.done
..............\sine.fit.eqn
..............\sine.fit.rpt
..............\sine.fit.summary
..............\sine.flow.rpt
..............\sine.map.eqn
..............\sine.map.rpt
..............\sine.map.summary
..............\sine.pin
..............\sine.pof
..............\sine.qpf
..............\sine.qsf
..............\sine.qws
..............\sine.sim.rpt
..............\sine.sof
..............\sine.tan.rpt
..............\sine.tan.summary
..............\sine.vhd
..............\sine.vwf
..............\talkback
..............\........\sine.asm.talkback.xml
..............\........\sine.fit.talkback.xml
..............\........\sine.map.talkback.xml
..............\........\sine.rpp.talkback.xml
..............\........\sine.sim.talkback.xml
..............\........\sine.tan.talkback.xml
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