Search - single MIPS

[Other] Ramtron_VRS51L2070_VRS51L3074_high_performance_MCU

Description: 单周期8051内核 8K铁电FRAM 56IO 4KRAM 40MIPS-single-cycle 8051 core 8K FRAM Ferroelectric 56IO 4KRAM 40MIPS
Platform: | Size: 422912 | Author: 华哥 | Hits:

[assembly language] V3K_Demo_Programs_rev1.0

Description: DEMO程序单周期8051内核 8K铁电FRAM 56IO 4KRAM 40MIPS -DEMO process single-cycle 8051 core 8K FRAM Ferroelectric 56IO 4KRAM 40MI PS
Platform: | Size: 274432 | Author: 华哥 | Hits:

[ARM-PowerPC-ColdFire-MIPS] mipssingelcycle

Description: mips single cycle implementation five files auxiliary pc data memory instruction memory adder forwarding
Platform: | Size: 5120 | Author: ramy | Hits:

[Other] singlecycle_mips

Description: single cycle mips design by verilog.
Platform: | Size: 18432 | Author: leejp | Hits:

[VHDL-FPGA-Verilog] singleCycleProc

Description: 简化的单时钟循环VHDL处理器.可以运行一些简单的mips指令，例如add, sub, and, or, slt, beq and j. -A simplified single cycle processor in VHDL. This processor can continuously execute some simple MIPS instructions which are lw, sw, add, sub, and, or, slt, beq and j.
Platform: | Size: 191488 | Author: 糖醋鱼 | Hits:

[VHDL-FPGA-Verilog] F10-Single-Cycle-MIPS

Description: This a verilog code of single cycle mips-This is a verilog code of single cycle mips
Platform: | Size: 587776 | Author: hualin | Hits:

[VHDL-FPGA-Verilog] mips

Description: 利用Verilog HDL硬件描述语言实现单周期MIPS_CPU设计。-Design of single-cycle MIPS_CPU
Platform: | Size: 958464 | Author: 金辉 | Hits:

[VHDL-FPGA-Verilog] project3

Description: mips single cycle cpu
Platform: | Size: 3273728 | Author: tran | Hits:

[VHDL-FPGA-Verilog] MIPS

Description: 用VHDL设计单周期的MIPS处理器,实现简单的指令-VHDL design with single-cycle MIPS processor, simple instructions
Platform: | Size: 69632 | Author: jialing | Hits:

[SCM] clock

Description: 功能要求：分离模块要求： 1）设计一个可以显示012345的显示电路，并利用单片机实现。 2）利用按键切换，然后显示ABCDEF 3）按键切换的动作，全部用串口进行通信。设计一个开关，当进行切换后，程序再进入主要要求。主要要求： (1) 显示准确的北京时间（时、分、秒），可用24小时制式； (2) 随时可以调校时间。 (3) 增加公历日期显示功能（年、月、日），年号只显示最后两位； (4) 随时可以调校年、月、日； (5) 允许通过转换功能键转换显示时间或日期。 (6) 所有按键需要通过串口自发自收来调校各种功能。 -Functional requirements: Separation module requires: 1) design a display can show 012,345 circuit, which uses single chip. 2) the use of key switching, and then display the ABCDEF 3) button to switch the action, all with the serial communication. Design of a switch, when to switch, the program re-entering the main requirement. Key requirements: (1) shows the exact Beijing (hours, minutes, seconds), available 24 hours format (2) can be adjusted at any time. (3) increasing the Gregorian calendar display function (year, month, day), era show only the last two (4) can always adjust the year, month, day (5) allows conversion by converting function key display time or date. (6) All keys need to adjust the serial port of spontaneous self-closing functions.
Platform: | Size: 10240 | Author: reaven | Hits:

[VHDL-FPGA-Verilog] mips-cpu

Description: 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
Platform: | Size: 117760 | Author: 王晓强 | Hits:

[VHDL-FPGA-Verilog] MIPS-processor-Verilog-code

Description: 原创，MIPS处理器Verilog源码，在FPGA实现单周期MIPS处理器，实现存储访问指令load word(lw)和store word(sw)，算术逻辑指令add、addi、sub、and、or和slt跳转指令branch equal(beq)和jump(j)-Original, achieves single-cycle MIPS processor MIPS processor Verilog source code, the FPGA, storage access instructions load word (lw) and store word (sw) arithmetic logic instructions add, addi, sub, and, or, and slt jump instructionbranch equal (beq, which) and jump (j)
Platform: | Size: 7168 | Author: ZLS | Hits:

[Software Engineering] mips--cpu

Description: 本文基于32位 MIPS CPU的体系架构，采用Xilinx ISE 9.1i软件，通过使用Verilog语言编写了32位MIPS单周期和多周期CPU的程序，完成了其逻辑设计并进行了仿真测试。-Based on a 32 MIPS CPU architectures using the Xilinx ISE 9.1i software, write a 32-MIPS, single cycle and multi-cycle CPU program completed its logic design and simulation tests using the Verilog language.
Platform: | Size: 314368 | Author: 朱祖建 | Hits:

[VHDL-FPGA-Verilog] single-CPU

Description: 单时钟CPU设计，spartan 3e板上试验通过，支持部分mips指令，内含示例mips代码及二进制文件-Single CPU clock design, spartan 3e board test passed, support some mips instruction, containing sample code and binary files mips
Platform: | Size: 15360 | Author: Chan Cheng | Hits:

[OS Develop] mips

Description: mips单周期支持add、sub(包括无符号、立即数)、跳转指令-mips single-cycle support add, sub (including unsigned immediate value), the jump instruction
Platform: | Size: 165888 | Author: 杨佳伟 | Hits:

[VHDL-FPGA-Verilog] mips

Description: 基于MIPS架构实现的单周期处理器，包含多种基本操作，验证方法是把自己的学号写进连续内存。-MIPS-based architecture for single-cycle processor, includes a variety of basic operations, authentication method is to learn their numbers written contiguous memory.
Platform: | Size: 1829888 | Author: 熊京魁 | Hits:

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[Other] Ramtron_VRS51L2070_VRS51L3074_high_performance_MCU

[assembly language] V3K_Demo_Programs_rev1.0

[ARM-PowerPC-ColdFire-MIPS] mipssingelcycle

[Other] singlecycle_mips

[VHDL-FPGA-Verilog] singleCycleProc

[VHDL-FPGA-Verilog] F10-Single-Cycle-MIPS

[VHDL-FPGA-Verilog] mips

[VHDL-FPGA-Verilog] project3

[VHDL-FPGA-Verilog] MIPS

[SCM] clock

[VHDL-FPGA-Verilog] mips-cpu

[VHDL-FPGA-Verilog] MIPS-processor-Verilog-code

[Software Engineering] mips--cpu

[VHDL-FPGA-Verilog] single-CPU

[OS Develop] mips

[VHDL-FPGA-Verilog] mips

[VHDL-FPGA-Verilog] mips

[assembly language] MIPS-Lite2

[source in ebook] mips

[Embeded-SCM Develop] single

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