Search - slave fifo fpga

[Windows Develop] USB-slavefifo

Description: 本组程序包括FPGA程序，固件程序和上位机程序，实现USB的数据传输功能，采用Slave Fifo模式，上位机程序利用Cypress公司提供的库函数进行开发
Platform: | Size: 383419 | Author: 林颖 | Hits:

[Windows Develop] USB-slavefifo

Description: 本组程序包括FPGA程序，固件程序和上位机程序，实现USB的数据传输功能，采用Slave Fifo模式，上位机程序利用Cypress公司提供的库函数进行开发-In this group include FPGA, firmware, procedures and PC procedures realize USB data transfer function, the Slave Fifo mode, host computer program using Cypress library functions provided by the company to develop
Platform: | Size: 5099520 | Author: 林颖 | Hits:

[Program doc] 68013_SlaveFIFO

Description: cy7c68013工作在SLAVE FIFO下的FPGA源代码，已经通过，Verilog编写-cy7c68013 slave fifo mode code ,written by hard ware language
Platform: | Size: 2151424 | Author: 杨瑞 | Hits:

[Books] usb

Description: 在高速的数据采集或传输中，目前使用较多的都是采用USB 2．0接口控制器和FPGA或DSP实现的，本设计在USB 2．0接口芯片CY7C68013的Slave FIFO模式下，利用FPGA作为外部主控制器实现对FX2 USB内部的FIFO进行控制，以实现数据的高速传输。该模块可普遍适用于基于USB 2．0接口的高速数据传输或采集中。-In the high-speed data acquisition or transmission, the currently used are based on more USB 2.0 interface controller and the FPGA or DSP implementation, the design USB 2.0 interface chip CY7C68013 of the Slave FIFO mode, the use of FPGA as a the external FX2 USB host controller to realize the internal FIFO control, in order to achieve high-speed data transmission. The module can be generally applied based on high-speed USB 2.0 interface, transfer or acquisition of data.
Platform: | Size: 894976 | Author: jiang_jennifer | Hits:

[VHDL-FPGA-Verilog] SLAVE_FIFO_16BITS

Description: 68013和FPGA通信含有68013 slave firmware 含有FPGA VHDL程序-communication between 68013 and FPGA including 68013 slave firmware including FPGA VHDL code
Platform: | Size: 1625088 | Author: xinsheng | Hits:

[Software Engineering] ThedesignofUniversalAsynchronousReceiverTransmitte

Description: 本课题所设计的UART支持标准的RS．232C传输协议，主要设计有发送模块、接收模块、线路控制与中断仲裁模块、Modem控制模块以及两个独立的数据缓冲区FIFO模块。该模块具有可变的波特率、数据帧长度以及奇偶校验方式，还有多种中断源、中断优先级、较强的抗干扰数据接收能力以及芯片内部自诊断的能力，模块内分开的接收和发送数据缓冲寄存器能实现全双工通信。除此之外最重要的是利用口模块复用技术设计数据缓冲区FIFO，采用两种可选择的数据缓冲模式。这样既可以应用于高速的数据传输环境，也能适合低速的数据传输场合，因此可以达到资源利用的最大化。-According to the characteristics of the UART and the portability advantage of FPGA designs，this paper puts forward an embedded UART design method based on FPGA chips．The design method includes description form of FSM and design approach of Top-Down．It’S good to take advantage of VHDL to program the slave module and top module of UART，and then integrate them into the interior of FPGA chip．In this case it improves not only the disadvantage of the traditional UART chips but also makes the whole system more compact and more reliable．
Platform: | Size: 5072896 | Author: mabeibei | Hits:

[VHDL-FPGA-Verilog] CoreSPI

Description: 数字电子设计fpga设计的spi接口的ip_core，可以直接用于在fpga设计，支持actel的fpga芯片，支持主从模式，fifo大小可选。-Fpga design of digital electronic design spi interface ip_core, fpga design can be directly used to support actel the fpga chip, support master-slave mode, fifo size options.
Platform: | Size: 1009664 | Author: zhangyujun | Hits:

[VHDL-FPGA-Verilog] CY7C68013FPGA

Description: USB控制芯片cy7c68013与FPGA通过slave fifo方式通信，块传输数据-USB controller chip and FPGA cy7c68013 way communication through the slave fifo, block data transfer
Platform: | Size: 961536 | Author: 张新 | Hits:

[VHDL-FPGA-Verilog] fpgaPfirmwarePpc

Description: 用FPGA做USB2.0通信的实验，完成SLAVE FIFO模式下的数据传输，里面包括固件程序，还有上位机（Ｃ＋＋）程序。-USB2.0 communication with the FPGA to do the experiment, complete the SLAVE FIFO mode data transmission, which includes firmware, and PC (C++) program.
Platform: | Size: 3322880 | Author: 王金凤 | Hits:

[VHDL-FPGA-Verilog] cpld-usb

Description: usb-fpga通讯，从cpld到usb协议芯片slave fifo的通讯过程指导。-The usb-FPGA communication from the CPLD to usb protocol chip slave FIFO communication process guidance.
Platform: | Size: 6144 | Author: 牟娇 | Hits:

[Other Embeded program] AN65974---FPGA-FX3-firmware

Description: FPGA与USB3.0芯片CYUSB3014的接口程序，作为slave fifo的固件代码-Source files for FPGA code and FX3 firmware
Platform: | Size: 3220480 | Author: joypoo | Hits:

[source in ebook] rd_wr_fifo_tb

Description: 68013 slave fifo 读写测试程序 fpga开发-68013 slave fifo
Platform: | Size: 1024 | Author: 周勇 | Hits:

[VHDL-FPGA-Verilog] SLAVE-FIFO-8BITS

Description: EZUSB FX2 的 SLAVE FIFO例程，包含8051的Firmware以及FPGA的FIFO控制代码 -EZUSB FX2 SLAVE FIFO sample program, including the 8051 firmware, and 8-bit VHDL slave FIFO interface code for FPGA
Platform: | Size: 1676288 | Author: Eddie | Hits:

[VHDL-FPGA-Verilog] EZ_USB_LOOPBACK

Description: 本程序：EZ-USB在slave fifo模式下，利用FPGA控制EZ-USB的数据读写-This program: EZ-USB in slave fifo mode, use the EZ-USB FPGA control data read and write
Platform: | Size: 2048 | Author: 陈培哲 | Hits:

[VHDL-FPGA-Verilog] 20131010-code

Description: fx2lp 68013 xilinx XC3s400 实现slave fifo通讯，包括68013的固件以及fpga的代码（verilog）。摸了好久才调试通过的，特共享出来解救苍生！-fx2lp 68013 xilinx XC3s400 slave fifo
Platform: | Size: 888832 | Author: jianhaoran | Hits:

[USB develop] SLAVE-FIFO-16BITS

Description: CY7C68013a的slavefifo的固件源代码，keil编写，以及使用FPGA向EP6端点写数据的verilog源代码，没有错误，可以编译成功!-CY7C68013a of slavefifo firmware source code, keil prepared using FPGA and write data to the endpoint EP6 verilog source code, no errors, you can compile successfully!
Platform: | Size: 223232 | Author: 向新铭 | Hits:

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[Windows Develop] USB-slavefifo

[Windows Develop] USB-slavefifo

[Program doc] 68013_SlaveFIFO

[Books] usb

[VHDL-FPGA-Verilog] SLAVE_FIFO_16BITS

[Software Engineering] ThedesignofUniversalAsynchronousReceiverTransmitte

[VHDL-FPGA-Verilog] CoreSPI

[VHDL-FPGA-Verilog] CY7C68013FPGA

[VHDL-FPGA-Verilog] fpgaPfirmwarePpc

[VHDL-FPGA-Verilog] cpld-usb

[Other Embeded program] AN65974---FPGA-FX3-firmware

[source in ebook] rd_wr_fifo_tb

[VHDL-FPGA-Verilog] SLAVE-FIFO-8BITS

[VHDL-FPGA-Verilog] EZ_USB_LOOPBACK

[VHDL-FPGA-Verilog] 20131010-code

[USB develop] SLAVE-FIFO-16BITS

[VHDL-FPGA-Verilog] SLAVE-FIFO-16BITS

[ARM-PowerPC-ColdFire-MIPS] FPGA

[VHDL-FPGA-Verilog] FPGA-Source-Code_VHDL

[VHDL-FPGA-Verilog] CCD_Array

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