Search - sobel verilog

[Graph program] sobel

Description: 图像边缘检测的VERILOG实现，能准确检测图像边缘
Platform: | Size: 590310 | Author: 李永杰 | Hits:

[VHDL-FPGA-Verilog] Sobel--Image_Filter_An_Image_filtering_VHDL

Description: Sobel--Image Filter (I). An Image filtering is made over data loaded into the on board RAM and presented on a VGA monitor.zip-Sobel-- Image Filter (I). An Image filteri Vi is made over the data loaded into RAM on board a nd presented on a VGA monitor.zip
Platform: | Size: 316416 | Author: 严刚 | Hits:

[Graph program] sobel

Description: 图像边缘检测的VERILOG实现，能准确检测图像边缘-Image Edge Detection of Verilog realize that can accurately detect image edge
Platform: | Size: 589824 | Author: 李永杰 | Hits:

[VHDL-FPGA-Verilog] Sobel

Description: Verilog code to calculate Sobel
Platform: | Size: 1024 | Author: lawrence | Hits:

[Software Engineering] sobel_filter

Description: implementation of SOBEL filter using FPGA board RC200 in handle-c
Platform: | Size: 4096 | Author: nishu | Hits:

[VHDL-FPGA-Verilog] sobel

Description: verilog sobel FPGA edge detection-Adopted verilog language realizes sobel edge detection in image processing algorithm
Platform: | Size: 10240 | Author: wkd | Hits:

[VHDL-FPGA-Verilog] Edge-detection

Description: 多个边缘检测sobel算子的verilog程序模块。-Multiple edge detection sobel operator verilog program modules
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilog] sobel

Description: Verilog代码实现Sobel算子，包括整个工程，仿真也有。。仿真表明该程序能实现Sobel 算子硬件实现-Verilog，Sobel Operator
Platform: | Size: 5014528 | Author: 蔡浩聪 | Hits:

[VHDL-FPGA-Verilog] DE2_CCD_sobel

Description: verilog编写的适用于fpga的3x3模板sobel滤波-verilog fpga prepared for the 3x3 template sobel filter
Platform: | Size: 5596160 | Author: 彭青艳 | Hits:

[VHDL-FPGA-Verilog] sobel2

Description: 新的sobel算子的FPGA实现。使用verilog语言，并调试通过~-The sobel operator new FPGA implementation. Verilog language, and debugging through to
Platform: | Size: 356352 | Author: abrams | Hits:

[Special Effects] grayscale

Description: 灰階(gray-scale)圖像處理(60*60 pixel)controller控制各個程式的地址以及開關，input_mem將資料讀進記憶體，grayscale將讀取資料像素的亮度以數值來表示，將24bit的像素化成四個8bit的值輸出。接著進入sobel，在此將前面的四個值乘上1或-1個別的相加，得出新的四個值，輸入進shiftcase進行threshold的判斷，大於threshold則表現出白色(255)，小於threshold則表現出黑色(0)，最後將結果存入記憶體out_mem。//Verilog-Implement digital image processing through HDL. Design a system to perform simple image processing using mask. Refer to the presentation slides “Simple Image Processor”.
Platform: | Size: 76800 | Author: sara kuo | Hits:

[Special Effects] sobel_edge_det

Description: 这是基于verilog语言的sobel检测的硬件语言设计，简单可用。-sobel verilog
Platform: | Size: 1024 | Author: zxc | Hits:

[Graph program] sobel

Description: 在FPGA中，采用verilog HDL语言实现图像处理算法sobel，仿真实验通过-In the FPGA using verilog HDL language image processing algorithms sobel, simulation experiment
Platform: | Size: 6255616 | Author: zhouhui | Hits:

[Other] sobel-with-verilog-language

Description: 用verilog实现sobel边缘检测算法-sobel edge detection with verilog language
Platform: | Size: 8192 | Author: 施楠 | Hits:

[VHDL-FPGA-Verilog] 中值滤波，sobel边沿检测，腐蚀，膨胀运算，Verilog

Description: 此程序为用Verilog编写的可实现中值滤波，sobel边沿检测，腐蚀膨胀运算，算法强大。
Platform: | Size: 524721 | Author: mazhonglei_468@163.com | Hits:

[ELanguage] MDL_SLX

Description: sobel edge detection using verilog code
Platform: | Size: 18432 | Author: ANDREW DENI X G | Hits:

[VHDL-FPGA-Verilog] DE2_70_D5M_LTM

Description: filtre de sobel sur fpga
Platform: | Size: 201728 | Author: jordra | Hits:

[VHDL-FPGA-Verilog] DE2_70 sobel

Description: DE2_70 sobel_dilationdsd
Platform: | Size: 237568 | Author: jordra | Hits:

[Graph program] sobel

Description: sobel算子的vhdl实现，顶层用verilog(vhdl implement on sobel)
Platform: | Size: 8192 | Author: 西风吹牛 | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:

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[Graph program] sobel

[VHDL-FPGA-Verilog] Sobel--Image_Filter_An_Image_filtering_VHDL

[Graph program] sobel

[VHDL-FPGA-Verilog] Sobel

[Software Engineering] sobel_filter

[VHDL-FPGA-Verilog] sobel

[VHDL-FPGA-Verilog] Edge-detection

[VHDL-FPGA-Verilog] sobel

[VHDL-FPGA-Verilog] DE2_CCD_sobel

[VHDL-FPGA-Verilog] sobel2

[Special Effects] grayscale

[Special Effects] sobel_edge_det

[Graph program] sobel

[Other] sobel-with-verilog-language

[VHDL-FPGA-Verilog] 中值滤波，sobel边沿检测，腐蚀，膨胀运算，Verilog

[ELanguage] MDL_SLX

[VHDL-FPGA-Verilog] DE2_70_D5M_LTM

[VHDL-FPGA-Verilog] DE2_70 sobel

[Graph program] sobel

[VHDL-FPGA-Verilog] sobel

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