Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - spi wishbone

Search list

[Com Port] simple_spi

Description: 一个简单的ＳＰＩ　ＩＰ核，SPI Core Specifications　可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. FEATURES: · Compatible with Motorola’s SPI specifications · Enhanced M68HC11 Serial Peripheral Interface · 4 entries deep read FIFO · 4 entries deep write FIFO · Interrupt generation after 1, 2, 3, or 4 transferred bytes · 8 bit WISHBONE RevB.3 Classic interface · Operates from a wide range of input clock frequencies · Static synchronous design · Fully synthesizable -a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
Platform: | Size: 473099 | Author: Jack | Hits:

[Com Port] simple_spi

Description: 一个简单的ＳＰＩ　ＩＰ核，SPI Core Specifications　可以从说明文档中找到！ The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. FEATURES: · Compatible with Motorola’s SPI specifications · Enhanced M68HC11 Serial Peripheral Interface · 4 entries deep read FIFO · 4 entries deep write FIFO · Interrupt generation after 1, 2, 3, or 4 transferred bytes · 8 bit WISHBONE RevB.3 Classic interface · Operates from a wide range of input clock frequencies · Static synchronous design · Fully synthesizable -a simple SPI IP core, SPI Core Specifications from documentation found! The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral In terface found on Motorola's M68HC11 family of CP Us. The Serial Peripheral Interface is a serial , synchronous communication protocol that're quires a minimum of three wires. FEATURES : Compatible with Motorola's SPI specificatio ns Enhanced Serial Peripheral Interf M68HC11 ace four entries deep FIFO read four entries deep wri te FIFO Interrupt generation after 1, 2, 3, 4 or 8 bit bytes transferred RevB.3 Cl WISHBONE assic interface Operates from a wide range of i nput clock frequencies Static synchronous de sign Fully synthesizable
Platform: | Size: 473088 | Author: Jack | Hits:

[Embeded-SCM Develop] spi_wishbone

Description: spi wishbone bus code
Platform: | Size: 49152 | Author: 磊 | Hits:

[VHDL-FPGA-Verilog] simple_spi.tar

Description: Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation. As with the SPI found in MC68HC11 processors the core features programmable clock phase [CPHA] and clock polarity [CPOL]. The core features an 8bit wishbone interface. Very simple, very small.
Platform: | Size: 574464 | Author: eldis | Hits:

[Other] spi_master

Description: SPI wishbone master and verification environment
Platform: | Size: 2506752 | Author: 王小墨 | Hits:

[VHDL-FPGA-Verilog] SPI_Wishbone_Controller

Description: FPGA SPI总线硬件描述语言Verilog下的实现-FPGA SPI bus under the Verilog hardware description language to achieve
Platform: | Size: 199680 | Author: deng | Hits:

[Other] spi_v

Description: 基于wishbone总线的spi串口控制器-a spi compilant serial port controller based on wishbone on-chip bus
Platform: | Size: 8192 | Author: wen | Hits:

[VHDL-FPGA-Verilog] spilicheng

Description: spi接口的wishbone总线的实现，能够实现spi控制器的基本功能，书上例程-spi interface wishbone bus, to achieve the basic functions of the spi controller to book routine
Platform: | Size: 2250752 | Author: 在 | Hits:

[VHDL-FPGA-Verilog] SPI

Description: Verilog编写的SPI程序，含英文原文档说明，很全的-The OpenCores simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. Enhancements to the original interface include a wider supported operating frequency range, 4 entries deep read and write FIFOs, and programmable transfer count dependent interrupt generation. The high compatibility with the M68HC11 SPI port ensures that existing software can use this core without major modifications. New software can use existing examples as a starting point. The core features an 8 bit wishbone interface.
Platform: | Size: 49152 | Author: 邓楠 | Hits:

[VHDL-FPGA-Verilog] simple_spi_latest.tar

Description: - 与摩托罗拉的SPI规格兼容 - 增强摩托罗拉MC68HC11串行外设接口 - 4项深读FIFO - 4项深写入FIFO - 中断后1代，2，3或4个转移字节 - 8位WISHBONE RevB.3经典界面 - 经营的输入时钟频率范围广泛 - 静态同步设计 - 完全可合成 - 130LUTs在Spartan-II，230在ACEX LCELLs的-- Compatible with Motorola s SPI specifications - Enhanced Motorola MC68HC11 Serial Peripheral Interface - 4 entries deep read FIFO - 4 entries deep write FIFO - Interrupt generation after 1, 2, 3, or 4 transfered bytes - 8 bit WISHBONE RevB.3 Classic interface - Operates from a wide range of input clock frequencies - Static synchronous design - Fully synthesizable - 130LUTs in a Spartan-II, 230 LCELLs in an ACEX
Platform: | Size: 575488 | Author: 张居林 | Hits:

[VHDL-FPGA-Verilog] SPI-SourceCode

Description: SPI Serial Peripheral Interface WISHBONE Controller SourceCode
Platform: | Size: 489472 | Author: horacedu | Hits:

[VHDL-FPGA-Verilog] eetop.cn_spi.tar

Description: 基于wishbone总线的SPI主设备代码(spi master based on wishbone bus)
Platform: | Size: 247808 | Author: 说给自己听 | Hits:

CodeBus www.codebus.net