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[Other resource] quartusII_clock DL : 0: vhdl语言开发，开发环境为QuartusII6.0和NIOS 6.0开发，是一个模拟交通灯的程序，其中用的芯片是stratix系列-vhdl language development, QuartusII6.0 development environment for the development and NIOS 6.0, is a simulated traffic signals procedures, which the chip is stratix Series
Update : 2008-10-13 Size : 6.85mb Publisher : 河南
[Other resource] quartusII_traffic DL : 0: 在quartusII平台开发的一个交通灯的控制程序，并在nios平台上可以使用，所用的芯片是Stratix
Update : 2008-10-13 Size : 6.79mb Publisher : 河南
[Other resource] LED47DISP DL : 0: 4-7segment led display Verilog code. Implemented at Stratix EP1S25 DSP development board.-4-7segment led display Verilog code. Impl emented at Stratix EP1S25 DSP development boar d.
Update : 2008-10-13 Size : 2.01kb Publisher : iamz
[Other resource] interpolation_FIR DL : 0: Interpolation FIR Design Example for Stratix Devices
Update : 2008-10-13 Size : 24.8kb Publisher : Jack
[Other resource] magnitude DL : 0: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Update : 2008-10-13 Size : 12.61kb Publisher : 郝晋
[VHDL-FPGA-Verilog] LED47DISP DL : 0: 4-7segment led display Verilog code. Implemented at Stratix EP1S25 DSP development board.-4-7segment led display Verilog code. Impl emented at Stratix EP1S25 DSP development boar d.
Update : 2025-02-17 Size : 2kb Publisher : iamz
[VHDL-FPGA-Verilog] interpolation_FIR DL : 0: Interpolation FIR Design Example for Stratix Devices
Update : 2025-02-17 Size : 24kb Publisher : Jack
[VHDL-FPGA-Verilog] magnitude DL : 0: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Update : 2025-02-17 Size : 12kb Publisher : 郝晋
[Program doc] StratixGX DL : 0: Stratix GX器件在SDH宽带交换中的应用-Stratix SDH serdes
Update : 2025-02-17 Size : 28kb Publisher : fnd
[VHDL-FPGA-Verilog] myAlteraLib DL : 0: myAltera的PCBLib库，包括Cyclone系列,Stratix系列，-myAlteraLib
Update : 2025-02-17 Size : 408kb Publisher : LaoY
[VHDL-FPGA-Verilog] stratix_handbook DL : 0: Altera 公司生产的FPGA系列中的高端产品stratix一代用户手册这个也能从Altera官方网站上下载。-Altera' s FPGA series production of high-end products stratix generation of user manuals that are downloaded from the Altera website.
Update : 2025-02-17 Size : 5.32mb Publisher : carris
[VHDL-FPGA-Verilog] stratix2_handbook DL : 0: Altera 公司生产的FPGA系列中的高端产品stratix二代用户手册这个也能从Altera官方网站上下载。-Altera' s FPGA series production of high-end products stratix second-generation user' s manual that is also downloaded from the Altera website.
Update : 2025-02-17 Size : 3.98mb Publisher : carris
[Software Engineering] STRATIX DL : 0: this document is related to architecture
Update : 2025-02-17 Size : 164kb Publisher : Salman Imam
[VHDL-FPGA-Verilog] stratixIII_3sl150_dev_TSE_SGMII_v1 DL : 0: 该程序实现altera开发板 stratix III 3S150通过以太网与pc之间通信。使用Quartus II和Nios II 设计。因为altera官方没有这块板子的正确网卡与pc通信的程序，-Overall This example works at 1000M/100M/10M Base SGMII mode on SIII 3S150 Kit. Designed by Quartus II/IP Cores/Nios II EDS v8.0 This is not an official released Design Example. It is only for your reference, but beyond the support area of ALTERA Mysupport.
Update : 2025-02-17 Size : 6.91mb Publisher : 杨庆育
[VHDL-FPGA-Verilog] FULLTEXT01 DL : 0: IMPLEMENTATION OF AN IEEE 802.11A TRANSMITTER IN VHDL FOR ALTERA STRATIX II FPGA
Update : 2025-02-17 Size : 239kb Publisher : bz
[Program doc] Stratix DL : 0: Stratix的器件介绍，用于初学者了解ALTERA的器件参数-the descripsion of Stratix
Update : 2025-02-17 Size : 4.21mb Publisher : robin
[Special Effects] Stratix-V-GX-Devboard DL : 0: altera 的Straix V GX开发板原理图，可供硬件设计人员借鉴参考。-Schimatics of Stratix V GX FPGA Development Kit Board，useful for fpga or high speed board designers.
Update : 2025-02-17 Size : 1.51mb Publisher : 张际朝
[Other] aic_audio DL : 0: Audio Interface for Stratix II DSP development kit
Update : 2025-02-17 Size : 475kb Publisher : AmrAshry
[VHDL-FPGA-Verilog] stratix-10-mx-product-table DL : 0: stratix 10 mx product table
Update : 2025-02-17 Size : 68kb Publisher : DrArmaggedon
[Documents] stratix-10-product-table DL : 0: Statix 10 product table
Update : 2025-02-17 Size : 75kb Publisher : DrArmaggedon

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