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[Other resource] 5bit-adder-subtracter

Description: 5 bits 的加法器與減法器合併電路之原始程式製作
Platform: | Size: 53393 | Author: dajen | Hits:

[VHDL-FPGA-Verilog] 5bit-adder-subtracter

Description: 5 bits 的加法器與減法器合併電路之原始程式製作 -5 bits of the adder circuit combined with the subtraction of the original browser program production
Platform: | Size: 53248 | Author: dajen | Hits:

[VHDL-FPGA-Verilog] Mars-EP1C6-F_code1

Description: 此包中为FPGA学习板中的基础实验代码.共包括8个实验源代码:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机和四位比较器.-In this package for the FPGA board to study the basis of the experiment code. A total of eight experiments, including source code: 8-bit priority encoder, multipliers, multi-way selector switch BCD binary code, adder, subtracter, simple state machine and 4 comparator.
Platform: | Size: 1099776 | Author: sunxh092 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 本代码为用VHDL语言设计实现加法器、减法器、乘法器，并提供了模块图，进行了波形仿真。-This code is for the use of VHDL Language Design and Implementation of adder, subtracter, multiplier, and provides a block diagram carried out a wave simulation.
Platform: | Size: 15360 | Author: 张霄 | Hits:

[VHDL-FPGA-Verilog] EDA1

Description: 完成一位二进制全减器的设计，采用文本输入法分别实现，分层设计，底层采用半加器和逻辑门实现。-Completion of a binary full subtracter design, implementation, respectively, using the text input method, hierarchical design, are based on half adder and logic gates.
Platform: | Size: 391168 | Author: 周旋 | Hits:

[VHDL-FPGA-Verilog] subber

Description: 完成一位二进制全减器的设计，采用原理图输入法和文本输入法分别实现，分层设计，底层由半加器（也用原理图输入法）和逻辑门组成-Completion of a binary full subtracter design, the use of schematic and text input method input method were realized, hierarchical design, the bottom of the half adder (also used schematic entry method) and the composition of logic gates
Platform: | Size: 115712 | Author: sxh | Hits:

[VHDL-FPGA-Verilog] hw1

Description: Using the schematic Design Entry Method, design a logic circuit that has two 2-bit inputs X and Y, a 1-bit input CinOrBin, and a 1-bit control input SubAddn. When the control input SubAddn is ‘0’, the logic circuit behaves as a 2-bit adder ( X + Y + CinOrBin ) with CinOrBin as the carry-in when the control input SubAddn is ‘1’ and the logic circuit behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with CinOrBin as the borrow-in. You must use Half-Adders and Half-Subtracters as building blocks to obtain a structured design. -Using the schematic Design Entry Method, design a logic circuit that has two 2-bit inputs X and Y, a 1-bit input CinOrBin, and a 1-bit control input SubAddn. When the control input SubAddn is ‘0’, the logic circuit behaves as a 2-bit adder ( X + Y + CinOrBin ) with CinOrBin as the carry-in when the control input SubAddn is ‘1’ and the logic circuit behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with CinOrBin as the borrow-in. You must use Half-Adders and Half-Subtracters as building blocks to obtain a structured design.
Platform: | Size: 365568 | Author: vinay | Hits:

[VHDL-FPGA-Verilog] hw2

Description: Using the VHDL Entry Method, design a logic circuit that behaves a 2-bit adder ( X + Y + CinOrBin ) with carry-in when the control input SubAddn is ‘0’ and behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with borrow-in when the control input SubAddn is ‘1’. -Using the VHDL Entry Method, design a logic circuit that behaves as a 2-bit adder ( X + Y + CinOrBin ) with carry-in when the control input SubAddn is ‘0’ and behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with borrow-in when the control input SubAddn is ‘1’.
Platform: | Size: 627712 | Author: vinay | Hits:

[SCM] ADDER

Description: .采用原理图输入法和文本输入法实现全减器，分层设计，底层由半加器（也用原理图输入法）和逻辑门组成； 2.给出此项设计的仿真波形； 3.选择实验电路进行验证, 由发光管指示显示结果。 -. The use of schematic and text input method input method to achieve full subtracter, hierarchical design, the bottom of the half adder (also used schematic entry method), and logic gates 2 shows the design of the simulation waveform 3. Select the experimental circuit to verify the result by the LED indicator is displayed.
Platform: | Size: 110592 | Author: daleli | Hits:

[VHDL-FPGA-Verilog] butterfly1

Description: FFT 蝶形处理器的VHDL代码，由一个加法器，一个减法器和一个实例化为组件的旋转因子乘法器ccmul组成-FFT butterfly processor VHDL code by an adder, a subtracter, and an instance of the component into the composition of the rotation factor multiplier ccmul
Platform: | Size: 1024 | Author: cxl | Hits:

[VHDL-FPGA-Verilog] quanjieqi

Description: 基于EDA开发系统箱上实现2位全减器的VHDL编程语言，附带波形仿真。-EDA development system based on the realization of two boxes full subtracter in VHDL programming language, with wave simulation.
Platform: | Size: 348160 | Author: 小熊 | Hits:

[VHDL-FPGA-Verilog] LIBRARY-IEEE

Description: 底层文件2：h_subber.VHD实现一位半减器 顶层文件：f_subber.VHD实现一位全减器 -The underlying file 2: h_subber.VHD-to achieve a half- Top-level file: f_subber.VHD the realization of a full subtracter
Platform: | Size: 3072 | Author: 燕子 | Hits:

[VHDL-FPGA-Verilog] Four-adder-of-subtracter

Description: 在max+plus II 的环境下设计4位全加器数字电路 使用vhdl语言，进行设计数字电路的RTL级电路 -Four full adder digital circuit design environment, max+ plus II RTL-level circuit, digital circuit design using vhdl language
Platform: | Size: 567296 | Author: 东方不败 | Hits:

[Other Embeded program] 11

Description: HSPICE 全加全减器设计 带波形仿真文件 超大规模集成电路设计-HSPICE full adder full subtracter design with VLSI design of the simulation waveform files
Platform: | Size: 191488 | Author: 邓烨 | Hits:

[Windows Develop] fVerrilog_Devr

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器，乘法器，多路选择器，二进制转BBCD码，加法器，减法器，简简单易懂状态机，四位比较器，7段数码管，i2c总线，lcd液晶LCD显示出来，拨码开关，串口，蜂鸣器，矩阵键盘，跑马灯，交通灯，数字时钟 可直接使用。 -Friends, I Jawen. See previous upload a CPLD Development Board VHDL source code quite popular, she will Verilog source together with contribution to everyone: eight priority encoder, multipliers, multiplexers binary switch the BBCD code, adder, subtracter, simple straightforward state machine, four comparators, 7-segment LED, i2c bus, lcd LCD LCD display, DIP switch, serial port, buzzer, matrix keyboard, Marquee, traffic lights, digital clock can be used directly.
Platform: | Size: 3170304 | Author: qtzx | Hits:

[VHDL-FPGA-Verilog] binary_adder_subtractor

Description: binary adder / subtracter in vhdl
Platform: | Size: 1024 | Author: sree | Hits:

[Program doc] v15-23

Description: paper related to adder/subtracter design using VHDL
Platform: | Size: 342016 | Author: Arun | Hits:

[VC/MFC] sub

Description: 用FGPA实现全减器的功能，并产生功能仿真波形。-With FGPA the full subtracter function, and generate functional simulation waveforms.
Platform: | Size: 342016 | Author: jiangcao | Hits:

[JSP/Java] FinalDesign

Description: 实现逻辑门电路的绘制以及运算。并且实现了加法器、减法器、乘法器、比较器等运算-Implementation of logic gate drawing and operation. And implement the adder, subtracter, multiplier, comparator and other operations
Platform: | Size: 778240 | Author: 张寅艳 | Hits:

[GDI-Bitmap] fdiv

Description: 用Quarters ii实现对减法器的仿真-In the Quarters ii realize the simulation of the subtracter
Platform: | Size: 313344 | Author: 赵艳 | Hits:
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