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[Other resource] Uart2

Description: uart的VHDL源代码，包括intface.VHD UART_RX_TAB.VHD UART_INT_TB.VHD等-uart VHDL source code, including intface.VHD UART_RX_TAB.VHD UART_INT_TB. Volume etc.
Platform: | Size: 43732 | Author: 罗辉 | Hits:

[VHDL-FPGA-Verilog] vhdl-2

Description:
Platform: | Size: 59392 | Author: lileiming | Hits:

[VHDL-FPGA-Verilog] Uart2

Description: uart的VHDL源代码，包括intface.VHD UART_RX_TAB.VHD UART_INT_TB.VHD等-uart VHDL source code, including intface.VHD UART_RX_TAB.VHD UART_INT_TB. Volume etc.
Platform: | Size: 43008 | Author: 罗辉 | Hits:

[VHDL-FPGA-Verilog] gh_uart_16550_080407

Description: FPGA开发中常用的串口模块，经过本人调试，非常实用-Commonly used in FPGA development serial module, after I debug, very useful
Platform: | Size: 16384 | Author: libin | Hits:

[Communication-Mobile] SC6600D_Sample

Description: 展讯SC6600D例程，包含定时器和串口通讯例子-Spreadtrum SC6600D routines, including timers and serial communication example
Platform: | Size: 27648 | Author: lihaitong | Hits:

[VHDL-FPGA-Verilog] uart.vhd

Description: this modul is serial send & resive for RS232
Platform: | Size: 1024 | Author: rez | Hits:

[VHDL-FPGA-Verilog] 03.EDK8.2

Description: 使用xilinx virtex4芯片，设计环境为EDK，其中包含uart,片外sram操作，flash操作，DDR SDRAM操作，MAC自发自收，audio，video等试验-Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-admission, audio, video and other tests
Platform: | Size: 22821888 | Author: 肖姗姗 | Hits:

[Software Engineering] uart_vhd

Description: Test Uart on board Nexys 2by VHD
Platform: | Size: 453632 | Author: Le Hoan | Hits:

[VHDL-FPGA-Verilog] uart16750

Description: UART 16750 source code for VHDL
Platform: | Size: 151552 | Author: maxshao | Hits:

[VHDL-FPGA-Verilog] TLC5510-VHDL

Description: （1）UART发送器VHDL程序 --文件名：transfer.vhd。 --功能：UART发送器。 --说明：系统由五个状态（x_idle,x_start,x_wait,x_shift,x_stop）和一个进程构成。 -(1) UART transmitter VHDL program- the file name: transfer.vhd.- Function: UART transmitter.- Description: The system consists of five states (x_idle, x_start, x_wait, x_shift, x_stop) and a process of composition.
Platform: | Size: 3072 | Author: pepsiprite | Hits:

[Program doc] UARTNX

Description: the simple codig in vhd of uart
Platform: | Size: 5120 | Author: pablommsgp | Hits:

[VHDL-FPGA-Verilog] uart-to-GPIO.vhd

Description: -- Filename ﹕ uart.vhd -- Author ﹕ZRtech -- Description ﹕串口接收与发送程序 -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证-- 程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位-- 8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波-- 特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接-- 受每一位bit的周期时间划分为8个时隙以使通信同步. -- Called by ﹕Top module -- Revision History ﹕10-5-20 -- Revision 1.0 -- Company ﹕ ZRtech Technology .Inc -- Copyright(c) 2010, ZRtech Technology Inc, All right reserved-- Filename: uart.vhd- Author: ZRtech- Description: serial port receive and transmit programs- the function of this module is to verify the basic realization and PC serial communication functions. Need to install one on the PC serial port debugging tool to verify- program function. Program implements a transceiver a 10 bit (ie, no parity bit) serial controller, 10 bit is a start bit- 8 data bits, 1 stop bit. Baud-law by the parameters defined in the program div_par decision to change the parameter can achieve the corresponding wave- special rates. Program is currently set div_par value is 0x145, corresponding to the baud rate is 9600. 8 times the baud rate by a clock to transmit or- by the cycle time of each bit is divided into eight time slots to the communication sync.- Called by: Top module- Revision History :10-5- 20- Revision 1.0- Company: ZRtech Technology. Inc- Copyright (c) 2010, ZRtech Technology Inc, All right reserved
Platform: | Size: 3072 | Author: hj | Hits:

[VHDL-FPGA-Verilog] wb_uart_latest.tar

Description: 实现一个一16750/16550 UART。该UART内核是完全基于另一个OpenCores的项目：UART_16750塞巴斯蒂安维特。 请找到有关于UART内核的文档。 该接口是现在有8位Wishbone总线兼容。 随着GHDL模拟器只需运行： ./ghdl_uart.bat 使用任何其他模拟器，开始模拟以下perl脚本必须运行之前： uart_test_stim.pl> FILENAME.TXT 其中，FILENAME.TXT是通用的“stim_file”选择内部wb8_uart_transactor.vhd的名称。 正确的模拟应退出并断言消息“模拟END”。-Implements a 16550/16750 UART. The UART core is fully based on another OpenCores project: UART_16750 by Sebastian Witt. Please find there the documentation regarding the Uart core. The interface is now compatible with a 8-bit WishBone bus. With GHDL simulator simply run: ./ghdl_uart.bat Using any other simulator, before starting the simulation the following perl script must be run: uart_test_stim.pl > filename.txt where filename.txt is the name selected in generic stim_file inside wb8_uart_transactor.vhd. A correct simulation should exit with an assertion message simulation END .
Platform: | Size: 21504 | Author: 包 | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart.vhd is module to communicate with uart
Platform: | Size: 1024 | Author: tariq | Hits:

[Other] uart_test

Description: uart vhd test file for xilinx
Platform: | Size: 3072 | Author: omid | Hits:

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