Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - usb1.1 vhdl

Search list

[Other resource] USB 1.1 IP-CORE和设计范例 VHDL源代码

Description: USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
Platform: | Size: 426278 | Author: ken | Hits:

[VHDL-FPGA-Verilog] USB 1.1 IP-CORE和设计范例 VHDL源代码

Description: USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
Platform: | Size: 425984 | Author: ken | Hits:

[Other] usb1.1

Description: USB 1.1的verilog代码，已通过fpga验证-USB 1.1 in Verilog code, has passed through FPGA verification
Platform: | Size: 63488 | Author: zys | Hits:

[USB develop] USBipcore

Description: usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
Platform: | Size: 155648 | Author: liu | Hits:

[VHDL-FPGA-Verilog] usb11

Description: 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。-Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
Platform: | Size: 414720 | Author: 戴求淼 | Hits:

[Other] usb_doc

Description: USB_DOC,详细描述了usb1.1协议-USB_DOC，it descibes usb
Platform: | Size: 134144 | Author: 龙哥 | Hits:

[VHDL-FPGA-Verilog] IPcore

Description: 非常有用的IP核资源，里面包含了JTAG,MEMORY,PCI，SDRAM和USB1.1等内容，期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us
Platform: | Size: 903168 | Author: 李同滨 | Hits:

[USB develop] usb11_phy_translation_latest.tar

Description: USB1.1 物理层实现 VHDL，opencore上也是可以下载的，是1.1的版本，比较简单，但是很实用，对于入门usb还是有帮助的-usb11_phy_translation_latest version
Platform: | Size: 7168 | Author: 姚 | Hits:

[USB develop] USB-1.1-IP-CORE-VHDL

Description: USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code
Platform: | Size: 425984 | Author: sxhfjgl010 | Hits:

[VHDL-FPGA-Verilog] usb_Phy

Description: usb1.1 VHDL源码，主要描述收发数据过程-usb1.1 the VHDL source code, description of the send and receive data process
Platform: | Size: 6144 | Author: | Hits:

[Software Engineering] USB1.1-VHDL

Description: USB PHY RX DPLL This source file may be used and distributed without restriction provided that this copyright statement is not removed from the file and that any derivative work contains the original copyright notice and the associated disclaimer.-USB PHY RX DPLL This source file may be used and distributed without restriction provided that this copyright statement is not removed from the file and that any derivative work contains the original copyright notice and the associated disclaimer.
Platform: | Size: 6144 | Author: LJ | Hits:

CodeBus www.codebus.net