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Search - verilog 16 bits

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[Other] BCD-int

Description: BCD码和16/32位有符号以及无符号整型数之间的转换-BCD and 16/32 bits signed and unsigned integer conversion between the
Platform: | Size: 1024 | Author: huhc | Hits:

[VHDL-FPGA-Verilog] mutip

Description: 16位乘法器 16位乘法器 -16-bit multiplier 16 multiplier 16 multiplier
Platform: | Size: 1024 | Author: | Hits:

[Other] lcd2tft

Description: convert lcd 4 bits to tft 16 bits.Writen verilog,Altera Quartus.
Platform: | Size: 816128 | Author: ulsonic | Hits:

[VHDL-FPGA-Verilog] cpu_16bit

Description: design cpu 16 bits by verilog HDL.
Platform: | Size: 1024 | Author: tommy | Hits:

[VHDL-FPGA-Verilog] 16_bits_CPU_verilog_code

Description: 利用Verilog设计的16位CPU的设计案例-the example of 16 bits CPU using verilog
Platform: | Size: 880640 | Author: 王惠娟 | Hits:

[Software Engineering] bai4

Description: a 16 bits counter using verilog
Platform: | Size: 1906688 | Author: atula136 | Hits:

[VHDL-FPGA-Verilog] wallace

Description: wallace tree 用于16位乘法器的verilog 的 wallace tree代码 -wallace tree verilog file. 16bit wallace tree adder.
Platform: | Size: 2048 | Author: Zachary | Hits:

[VHDL-FPGA-Verilog] dds

Description: 用Verilog语言实现基于dds技术的余弦信号发生器，其输出位宽为16比特-Dds with the Verilog language technology based on the cosine signal generator, the output bit width is 16 bits
Platform: | Size: 8192 | Author: xiaobai | Hits:

[VHDL-FPGA-Verilog] MSB_search_verilog

Description: 使用Verilog实现16位数据最高有效位的查找-use verilog to search msb of 16 bits data
Platform: | Size: 131072 | Author: fc | Hits:

[VHDL-FPGA-Verilog] bk

Description: 16位Brent-Kung加法器的verilog代码-the verilog code of the 16 bits of the Brent-Kung s adder
Platform: | Size: 1024 | Author: zxb | Hits:

[VHDL-FPGA-Verilog] 5-15

Description: 用verilog语言实现基于DDS技术的余弦信号发生器，其输出位宽为16比特-Verilog language cosine signal generator based on DDS technology, the output bit width is 16 bits
Platform: | Size: 7168 | Author: 张山 | Hits:

[VHDL-FPGA-Verilog] addercs16.v

Description: 这是自己写的 16 bits carry select adder 的verilog的代码，如果有用fell free to download-It is 16 bits verilog write their own code to carry select adder, if a useful fell free to download
Platform: | Size: 1024 | Author: liuyang | Hits:

[Other Embeded program] FIFO1

Description: 给出一个位宽16比特，深度为10的异步FIFO的设计，并要求给出空或满的指示信号。要求用Verilog HDL语言设计，并编写测试激励，以及用Modelsim进行功能仿真，验证设计正确性。10个16位的数据　(FIFO的宽度：也就是英文资料里常看到的THE  WIDTH，它指的是FIFO一次读写操作的数据位，就像MCU有8位和16位，ARM 32位等等。FIFO的深度：THE DEEPTH，它指的是FIFO可以存储多少个N位的数据（如果宽度为N）。如一个8位的FIFO，若深度为8，它可以存储8个8位的数据，深度为12，就可以存储12个8位的数据。)-Give a 16 bits wide, depth of 10 asynchronous FIFO design, and requires giving empty or full instructions signal. Request using Verilog HDL language design, and the writing test, and simulation using Modelsim function, validate design is correct. 10 16 bits of data (THE WIDTH of THE FIFO, namely information in English often see THE WIDTH, it refers to a FIFO data read and write operations, as has 8 bit or 16 bit MCU, ARM 32-bit and so on. THE depth of FIFO: THE DEEPTH, it refers to THE FIFO can store many N bits of data (if THE WIDTH is N). If an 8-bit FIFO, if THE depth of 8, it can store 8 8 bits of data, THE depth of 12, 12 8 bits of data to be stored.)
Platform: | Size: 33792 | Author: 江燕子 | Hits:

[Program doc] DCC2010-FPGA-CPU16ASM-DCC

Description: cpu verilog 16 bits to control radio software
Platform: | Size: 81920 | Author: olivier | Hits:

[VHDL-FPGA-Verilog] spi

Description: 通过SPI接口给一段位宽16位长度为8的配置寄存器进行赋值。位宽为16 表示存储的数据信息位数为16，长度为8，则代表的是寄存器的深度为8。 在输入第一位数据时，定义一个计数器count，以判断目前接收了几个数据。当接收到第8位时，后六位为地址，前两位用于判断，10表示读操作，11表示写操作，进入读写操作后仍需计数，以便判断何时读完或写完，当count=24时为读写操作完毕。(Through the SPI interface to a 16 bit length 8 configuration register assignment. Width 16 digits represent the information stored for 16, length 8, is the representative of the register depth is 8. When the first bit of data is entered, a counter, count, is defined to determine the number of data received at the present time. When eighth bits are received, the 6 bits are the addresses, the first two bits are used for judgement, 10 is the read operation, 11 is the write operation, and it still needs to count after entering the read and write operation, so as to decide when to read or write, and when count=24 is read and write.)
Platform: | Size: 1024 | Author: 雪宝y | Hits:

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