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[VHDL-FPGA-Verilog] freqm

Description: a simple implementation of a frequency meter with the BCD-counter and the 7-segment LED display
Platform: | Size: 12288 | Author: wangfeng | Hits:

[SCM] 16bit_display8bitLED

Description: Abstract七段显示器在DE2可当成Verilog的console，做为16进位的输出结果。Introduction使用环境：Quartus II 7.2 SP1 + DE2(Cyclone II EP2C35F627C6)简单的使用switch当成2进位输入，并用8位数的七段显示器显示16进位的结果。-Abstract Seven-Segment Display as Verilog to DE2 at the console, as 16 of the output binary. Introduction to use the environment: Quartus II 7.2 SP1+ DE2 (Cyclone II EP2C35F627C6) the use of a simple switch as a binary input 2, and paragraph 8-digit binary display 16 results.
Platform: | Size: 7168 | Author: 王媛媛 | Hits:

[VHDL-FPGA-Verilog] 7-segment

Description: VHDL Design of BCD to 7-segment decoder using PROM
Platform: | Size: 60416 | Author: FATIMA | Hits:

[Technology Management] segment

Description: 7 segment display using verilog interfacing fpga and 7 segment display
Platform: | Size: 311296 | Author: kripa | Hits:

[VHDL-FPGA-Verilog] demtang09

Description: the proramme is created to be examble to leran verilog programming. it s porpuse is crease the number is 7-segment from 0 to 9.
Platform: | Size: 321536 | Author: connit1986 | Hits:

[VHDL-FPGA-Verilog] dem4bit_hienthi

Description: the verilog source code for being an examble to counts 4-bit number and display in 7-segment.
Platform: | Size: 318464 | Author: connit1986 | Hits:

[VHDL-FPGA-Verilog] seven_seg

Description: Verilog, 7segment, ISE
Platform: | Size: 9216 | Author: asdasd | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙，秒，分。 有开始，暂停，复位功能。 学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube showed the delicate, seconds, minutes. Has started, pause, reset. Learning VerilogHDL classic example of adding a display.
Platform: | Size: 571392 | Author: alvin | Hits:

[VHDL-FPGA-Verilog] chengfaqi.doc

Description: 设计一个两个5位数相乘的乘法器。用发光二极管显示输入数值，用7段显示器显示结果。乘数和被乘数分两次输入(verilog语言实现)-Design a multiplier of two 5-digit multiplication. Enter the value with the light-emitting diode display, with 7-segment display shows the results. Multiplier and the multiplicand input twice (verilog language)
Platform: | Size: 370688 | Author: huanhuan | Hits:

[VHDL-FPGA-Verilog] digital-tube

Description: 实现开发板上的数码管静态循环显示0~F。通过这个实验，掌握采用Verilog HDL语言编程实现7段数码管显示译码器的方法。-The digital realization of the development board cycling static display 0 ~ F. Through this experiment, using Verilog HDL language to master programming 7-segment display decoder method.
Platform: | Size: 310272 | Author: 松竹 | Hits:

[VHDL-FPGA-Verilog] LED_7seg

Description: FPGA的7段数码管程序，用verilog编写，很好的程序，不要错过啊-The 7-segment FPGA program written with verilog, very good program, do not miss ah
Platform: | Size: 220160 | Author: xuxing | Hits:

[VHDL-FPGA-Verilog] 7duanshumaguandejingtaixianshi

Description: 采用Verilog语言编写实现7段数码管的静态显示，经过CPLD开发板验证，程序正确-Verilog language used to achieve a static 7-segment display, after a CPLD development board verification, the program correctly
Platform: | Size: 125952 | Author: wanghong | Hits:

[VHDL-FPGA-Verilog] dianzimimasuo

Description: 采用verilog设计，7段数码管进行输入的显示，在DE-2平台上进行密码锁的实现。-Using verilog design, 7-segment LED display for input in the DE-2 platform on the lock implementation.
Platform: | Size: 1024 | Author: 结界小神 | Hits:

[SCM] hex2led

Description: 在quantusII环境下采用verilog HDL语言编辑的7段译码器HEX2LED设计 -In quantusII environment using verilog HDL language editors design 7-segment decoder HEX2LED
Platform: | Size: 4661248 | Author: scu | Hits:

[VHDL-FPGA-Verilog] digital_7

Description: Verilog七段数码管显示控制程序，已经在实验板上测试通过。-Verilog seven-segment LED display control program, the board has been tested in the experiment.
Platform: | Size: 445440 | Author: 吴平 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个可以综合的Verilog 7段秒表实例。上海交大微电子学院课程作业。-An example Verilog project. 7-segment
Platform: | Size: 2048 | Author: 123123 | Hits:

[assembly language] UART_RS232(verilog)

Description: /本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于全双工工作状态，按动key2，FPGA/CPLD向PC发送“21 EDA"KEY1是复位按键。字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向FPGA/CPLD发送0-F的十六进制数据，FPGA接受后显示在7段数码管上。-/ This module function is to verify that the basic serial communication functions and PC. A serial debugging tools to verify the functionality of the program needs to be installed on the PC. Implementation of a transceiver a 10 bit (ie no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Serial port baud rate law decided the procedures defined div_par parameters, the baud rate can change the parameters. The procedures set div_par the value is 0x145, corresponding to the baud rate is 9600. Eight times the baud rate clock to send or accept every bit of the cycle time is divided into eight time slots so that the communication synchronization. Program of work process: the serial port in full-duplex state, pressing key2 the FPGA/CPLD sent to the PC " 21 EDA" KEY1 reset button. Hexadecimal data string (serial debugging tool set to accept the way the ASCII code) 0-F PC may at any time be sent to the FPGA/CPLD, FPGA accepted displayed on the 7-segment LED
Platform: | Size: 600064 | Author: 饕餮小宇 | Hits:

[VHDL-FPGA-Verilog] 7duanyimaguan-Verilog-HDL

Description: 7段译码管的Verilog HDL程序，希望对大家有用-7 segment decoder tube Verilog HDL procedures
Platform: | Size: 10240 | Author: 罗康 | Hits:

[VHDL-FPGA-Verilog] segment

Description: 基于verilog xilinx spartan 的7段管显示-7-segment tube display based on verilog xilinx spartan
Platform: | Size: 289792 | Author: hanbojiang | Hits:

[assembly language] Verilog源代码

Description: 多种基本功能的Verilog代码实现，包括多路选择器，二进制到BCD码转换，二进制到格雷码转换，7段译码器，8位数据锁存器，移位寄存器等等多种功能。(Verilog code implementation of a variety of basic functions, including multiplexer, binary to BCD code conversion, binary to Gray code conversion, 7-segment decoder, 8-bit data latch, shift register and many other functions.)
Platform: | Size: 18432 | Author: MMK1 | Hits:
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