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Search - verilog LVDS

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[Other resource] diff_io_top

Description: LVDS的应用的Verilog HDL例子程序，由altera公司提供。
Platform: | Size: 527848 | Author: wangyunshann | Hits:

[VHDL-FPGA-Verilog] diff_io_top

Description: LVDS的应用的Verilog HDL例子程序，由altera公司提供。-LVDS Application of Verilog HDL examples of procedures provided by the altera.
Platform: | Size: 527360 | Author: wangyunshann | Hits:

[VHDL-FPGA-Verilog] xapp622

Description: 644 MHz SDR LVDS 发射器/接收器(verilog and doc)-644-MHz SDR LVDS Transmitter/Receiver
Platform: | Size: 355328 | Author: wicky | Hits:

[VHDL-FPGA-Verilog] xapp860

Description: 16通道DDR的LVDS接口（VHDL,Verilog and doc）-16-Channel, DDR LVDS Interface with Real-Time Window Monitoring
Platform: | Size: 650240 | Author: wicky | Hits:

[Data structs] hdl

Description: 对lvds的结构用verilog和vhdl代码进行了详细的描述-The structure of the lvds with verilog and vhdl code described in detail
Platform: | Size: 21504 | Author: LUCAS | Hits:

[VHDL-FPGA-Verilog] lvds

Description: 文章介绍了lvds技术在硬件设计中的原理和应用，先已被广泛应用-This paper introduces lvds in hardware design and application of the principle, first has been widely used
Platform: | Size: 89088 | Author: wang | Hits:

[VHDL-FPGA-Verilog] LIP1401CORE_IO_LVDS

Description: IO LVDS VHDL & Verilog code
Platform: | Size: 35840 | Author: jc | Hits:

[VHDL-FPGA-Verilog] 7_1LVDS_serilizer

Description: 7:1LVDS编码 为LVDS方面需求的人提供参考设计，很高兴- This VHDL or Verilog source code is intended as a design reference which illustrates how these types of functions can be implemented. It is the user s responsibility to verify their design for consistency and functionality through the use of formal verification methods.
Platform: | Size: 1024 | Author: 大方的 | Hits:

[VHDL-FPGA-Verilog] LVDS-application-Verilog-HDL-code

Description: LVDS的应用的Verilog HDL例子程序-LVDS example of the application procedures for the Verilog HDL
Platform: | Size: 421888 | Author: vico | Hits:

[VHDL-FPGA-Verilog] LKB001-U1-LK650-06

Description: 16通道高速DI数据采集模块程序，采用verilog 编写，quartus，cyclone EP1C3T1-high LVDS comm DI module hollysys bei jing quartus verilog
Platform: | Size: 40960 | Author: mycjj | Hits:

[Special Effects] MATLABtoISEtoCOE

Description: 艾法斯产品lvds口信号输出下变频程序，网上这方面的资料比较少，verilog主程序-Aeroflex products lvds output port signal downconversion process this information online is relatively small, verilog main
Platform: | Size: 75776 | Author: lvhenan | Hits:

[Other] test_3035C

Description: 成功接收艾法斯产品lvds信号的verilog程序，网上介绍比较少，希望有所帮助-Aeroflex products successfully received lvds signal verilog program, online presentation is relatively small, I hope to help
Platform: | Size: 9042944 | Author: lvhenan | Hits:

[Other] vhdl

Description: verilog for LVDS altera stratix4
Platform: | Size: 53248 | Author: daniele | Hits:

[VHDL-FPGA-Verilog] LVDS_SRC

Description: 实现LDVS接口数据接收 含有协议结构以及处理-lvds Verilog 512 frame
Platform: | Size: 444416 | Author: 王长友 | Hits:

[Picture Viewer] 7_to_1-LVDS-dispaly-from-FLASH

Description: 该代码是基于verilog 实现的代码，可以用于对接受1080P的LVDS视频数据并处理后显示到各种规格的LCD屏幕上，且支持从FLASH中读取BMP的图片数据并实时显示到LCS屏幕-The code is based on the code verilog achieve, it can be used for receiving LVDS 1080P video and data processing displayed on a variety of LCD screen, and support for reading data the FLASH BMP images and real-time display to the LCS screen
Platform: | Size: 104448 | Author: albert | Hits:

[Special Effects] LVDS_to_AXIS

Description: 8路串行lvds转单路并行axistream(8 single-pathLVDS to 1parallel AXI_Stream)
Platform: | Size: 3072 | Author: Impmx | Hits:

[Other Embeded program] Altera-LVDS_IP

Description: 自己总结的Altera_LVDS的IP核的设计及仿真分析，已在实际工程中应用到，并且带有源代码和仿真代码，总结的文档，非常有用。(My summary of the Altera_LVDS IP kernel design and simulation analysis, has been applied in practical engineering, and with source code and simulation code, summary of the document, very useful.)
Platform: | Size: 3191808 | Author: 何河 | Hits:

[Other] lvds

Description: XILINX 官方的LVDS IP核，亲测可用。。。。。(XILINX official LVDS IP kernel, pro test available.....)
Platform: | Size: 282624 | Author: shanyuan001 | Hits:

[Video Capture] Lvds_Receiver

Description: 基于FPGA实现1080p的LVDS 7:1接收程序(Implementation of 1080p LVDS 7:1 receiving program based on FPGA)
Platform: | Size: 2048 | Author: anzhi2020 | Hits:

[VHDL-FPGA-Verilog] LVDS

Description: 实现了LVDS的发送和接收，本例程增加了握手信号实现，没有用serdes(The sending and receiving of LVDS are realized)
Platform: | Size: 4096 | Author: E=MC2 | Hits:
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