Search - verilog O

[SCM] bcd_conv

Description: convert.asm: 1.From ASCII resp. BCD to binary 2.From binary to ASCII resp. BCD 3.From binary to Hex-ASCII Bin_Bcd.c: uchar BcdToBin(uchar val) uchar BinToBcd(uchar val) -convert.asm : 1.From ASCII resp. BCD 2.From binary to binary t o ASCII resp. BCD 3.From binary to Hex-ASCII Bin _Bcd.c : uchar BcdToBin (uchar val) uchar BinToBcd (uch ar val)
Platform: | Size: 5120 | Author: jack | Hits:

[Graph Drawing] Scan_T

Description: 自己写的一个对PC并口进行的操作程序，以及对数据的读入后，进行的波形显示。（需要硬件支持 D24/56 PCI i/o接口板）-himself wrote a parallel port on PC operating procedures, and to read into the data, the waveform shows. (D24/56 need hardware support PCI i/o interface board)
Platform: | Size: 92160 | Author: zhouwj | Hits:

[source in ebook] OVL

Description: OVL——基于断言的verilog验证 Verilog数字系统设计:RTL综合、测试平台与验证-OVL- assertion-based verification of Verilog Verilog digital system design: RTL synthesis, test and verification platform
Platform: | Size: 69632 | Author: | Hits:

[Other] Verilog

Description: verilog的简要教程基本逻辑门，例如a n d、o r和n a n d等都内置在语言中。 • 用户定义原语（ U D P）创建的灵活性。用户定义的原语既可以是组合逻辑原语，也可以是时序逻辑原语。 • 开关级基本结构模型，例如p m o s 和n m o s等也被内置在语言中。-Verilog tutorial briefly the basic logic gates, such as and, or and NAND are built in the language. • user-defined primitives (UDP) to create flexibility. User-defined primitives are the combinational logic can be the original language may also be a temporal logic primitives. • The basic structure of switch-level models, such as PMOS and NMOS are also being built in the language.
Platform: | Size: 4169728 | Author: 阿春 | Hits:

[VHDL-FPGA-Verilog] S3E_AnalogIO

Description: it is a analog i/o interface written in verilog .it will work on spartan 3 xilini devices.
Platform: | Size: 2048 | Author: ali | Hits:

[Crack Hack] BasicRSA_latest.tar

Description: RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman in 1977. Every user have a pair of key, public key and private key. Public key (e) . You may choose any number for e with these requirements, 1< e <Æ (n), where Æ (n)= (p-1) (q-1) ( p and q are first-rate), gcd (e,Æ (n))=1 (gcd= greatest common divisor). Private key (d). d=(1/e) mod(Æ (n)) Encyption (C) . C=Mª mod(n), a = e (public key), n=pq Descryption (D) . D=C° mod(n), o = d (private key- RSA ( Rivest Shamir Adleman )is crypthograph system that used to give a secret information and digital signature . Its security based on Integer Factorization Problem (IFP). RSA uses an asymetric key. RSA was created by Rivest, Shamir, and Adleman in 1977. Every user have a pair of key, public key and private key. Public key (e) . You may choose any number for e with these requirements, 1< e <Æ (n), where Æ (n)= (p-1) (q-1) ( p and q are first-rate), gcd (e,Æ (n))=1 (gcd= greatest common divisor). Private key (d). d=(1/e) mod(Æ (n)) Encyption (C) . C=Mª mod(n), a = e (public key), n=pq Descryption (D) . D=C° mod(n), o = d (private key
Platform: | Size: 5120 | Author: nb | Hits:

[VHDL-FPGA-Verilog] DMA_8237A

Description: 经典DMA控制器8237A的VHDL设计，对设计DMA控制器有很高的参考价值。-Classic DMA controller 8237A of the VHDL design, the design of the DMA controller has a high reference value.
Platform: | Size: 12288 | Author: neversee | Hits:

[VHDL-FPGA-Verilog] vmachine

Description: Verilog code for vending machine.. Description: Vending machine ll take two quarters and distribute one of the two flavors of juice(apple or orange). Inputs: • Q : A quarter has been inserted. • O : orange juice button is pressed. • A : apple juice button is pressed. • C : return the change. Outputs: • DO : distribut orange juice. • DA : distribute Apple juice • N : do nothing • R : return a quater-Verilog code for vending machine.. Description: Vending machine ll take two quarters and distribute one of the two flavors of juice(apple or orange). Inputs: • Q : A quarter has been inserted. • O : orange juice button is pressed. • A : apple juice button is pressed. • C : return the change. Outputs: • DO : distribut orange juice. • DA : distribute Apple juice • N : do nothing • R : return a quater
Platform: | Size: 8192 | Author: deepa | Hits:

[Editor] t4

Description: Explain the very good teaching Ve failed to translate miller overall lack of success of verilog language miller decoding Miller verilog language decoder o 4 Multiplier VHDL language design DRAM Controller verilog file
Platform: | Size: 2048 | Author: xxxx | Hits:

[VHDL-FPGA-Verilog] XILINX

Description: Verilog汇编很牛叉 O(∩_∩)O哈哈哈~-Verilog
Platform: | Size: 1024 | Author: 好古子 | Hits:

[Other] deep_LabVIEW_FPGA

Description: NI 通过LabVIEW FPGA 模块和可重复配置I/O(RIO)硬件设备，为测量和控制系统中整合FPGA 技术的灵活性提供了直观且现成可用的解决方案。您可以使用LabVIEW图形化编程定义FPGA 芯片上的逻辑功能，您不需要任何的有关底层硬件描述语言(HDLs)的知识，如VHDL 或是Verilog，也不需要了解板卡级硬件设计，就可以将FPGA 芯片嵌入到NI 可重复配置I/O 系列硬件目标当中。另外，LabVIEW还可以让您轻松地集成图象采集/分析、运动控制，以及CAN 和RS232 等工业通信功能。-Through the LabVIEW FPGA Module and NI reconfigurable I/O (RIO) hardware device, for measurement and control systems integrate the flexibility of FPGA technology provides the intuitive and readily available solution. You can use the LabVIEW graphical programming custom FPGA logic functions on a chip, you do not need any of the underlying hardware description languages (HDLs) knowledge, such as VHDL or Verilog, do not need to understand the board-level hardware design, it can be FPGA chip embedded into the NI reconfigurable I/O family of hardware Goals. In addition, LabVIEW also allows you to easily integrate image capture/analysis, motion control, as well as CAN and RS232 communication industries.
Platform: | Size: 274432 | Author: 侯yl | Hits:

[VHDL-FPGA-Verilog] source

Description: 包含了verilog hdl实验的很多源代码\(^o^)/~-Contains a verilog hdl a lot of experimental code \ (^ o ^)/~
Platform: | Size: 56320 | Author: annoby | Hits:

[VHDL-FPGA-Verilog] Writing-Testbenches-using-System-Verilog.tar

Description: Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I s and O s to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all.
Platform: | Size: 2775040 | Author: ynona | Hits:

[VHDL-FPGA-Verilog] 86verilog

Description: 以FPGA 芯片为平台构建了数字信号滤波实时处理模块, 给出了 50Hz 陷波器的切比雪夫Ê 型 IIR 数字滤波器 4 阶级联的结构, 提出了对滤波器系数量化的逼近方法, 完成了基于 FPGA 的陷波器实现, 并成功地实现了对含有工频 50Hz 噪声干扰的心电信号的滤波处理, 通过与M at lab 计算所得到的滤波处理效果进行比较分析, 结果表明: 基于FPGA 采用切比雪夫Ê 型 4 级级联结构的 IIR 数字滤波器的误差满足设计要求-　W ith the development of the techno logy of VL S I, the techno logy fo r digital signal p rocessing has developed rap idly . In th is paper, the arch itecture of 50Hz four th2 o rder Chebyshev′ s ModelÊ digital f ilter is show n . In the same t i me, themethod fo r f ilter coeff icient quant if icat i on is p resented . How ever, the f ilter based on FPGA is i mp lemented . The f ilter can p rocess digital signal successfully and its perfo rmance sat isf ies w ith design requirement .
Platform: | Size: 15360 | Author: 任伟 | Hits:

[VHDL-FPGA-Verilog] dw8051-used-in-FPGA

Description: 自己下载的dw8051核，并在atlys fpga开发板上运行成功。其中rom和ram都已经生成，4个并行I/O口也有。编程语言是verilog。另外，还有hex转in文件的小软件，以及Uedit这个文本编辑器，它是用来给dw8051的rom载入程序的。-The the dw8051 nuclear, download and run atlys fpga development board. Rom and ram have been generated, there are four parallel I/O port. The programming language is verilog. In addition, there are small software to the hex turn in documents, and Uedit text editor, it is used to dw8051 rom loaded program.
Platform: | Size: 29199360 | Author: ayading826 | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list