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Description: 交通灯控制电路 一、 设计任务与要求 1．设计一个十字路口的交通灯控制电路，要求甲车道和乙车道两条交叉道路上的车辆交替 运行，每次通行时间都设为25秒； 2．要求黄灯先亮5秒，才能变换运行车道； 3．黄灯亮时，要求每秒钟闪亮一次 。 二、实验预习要求 1．复习数字系统设计基础。 2．复习多路数据选择器、二进制同步计数器的工作原理。 3．根据交通灯控制系统框图，画出完整的电路图。-a control circuit design tasks and requirements 1. Design a crossroads of traffic lights control circuit, and requested a B lane cross-road of two lanes of traffic on the turn of operation, each time prevailing Set 25 seconds; 2. Asked yellow first-five seconds, can transform running lanes; 3. Bright yellow light, flashing a request per second. Two experimental rehearsal requirements 1. Review of digital systems design basis. 2. Review of Multiple Choice of data, binary synchronous counter to the principle. 3. According to the traffic light control system block diagram to depict the integrity of the circuit.
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Author: 刘鹏 |
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Description: SystemC片上系统设计的源代码：
书籍介绍：
SystemC是被实践证明的优秀的系统设计描述语言，它能够完成从系统到门级、从软件到硬件、从设计到验证的全部描述。SystemC 2.01已作为一个稳定的版本提交到IEEE，申请国际标准。
本书为配合清华大学电子工程系SystemC相关课程的教学而编写。全书分9章，内容包括：硬件描述语言的发展史；SystemC出现的历史背景和片上系统设计方法学概述；SystemC的基本语法；SystemC的寄存器传输级设计和SystemC的可综合语言子集，以及根据作者设计经历归结的RTL设计准则和经验；接口、端口和通道等SystemC行为建模实例——片上总线系统；SystemC与VHDL/Verilog HDL的比较；SystemC的验证标准和验证方法学；SystemC开发工具SystemC_win、WaveViewer等，以及使用MATLAB进行SystemC算法模块的验证。每一章都精心编写了课后习题以配合教学的需要。
本书可作为大学电子设计自动化（EDA）相关课程教材，也可供电子工程技术人员作为SystemC设计、应用开发的技术参考书。本书丰富的实例源代码特别适合初学者根据内容实际运行、体会，举一反三，以掌握SystemC进行应用系统设计。 -SystemC system on chip design source : books introduced : SystemC has been proven in practice is an excellent system design description language, it can be completed from the system level to the door, from hardware to software, from design to verification of all description. SystemC has 2.01 as a stable version submitted to the IEEE, the application of international standards. The book to tie in electronic engineering at Tsinghua University SystemC related courses and preparation of teaching. Book nine chapters, including : hardware description language development history; SystemC is the historical background and system-on-chip design methodology outlined; SystemC basic grammar; SystemC register-transfer-level design and synthesis of SystemC language subset, as well as design experience b
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Author: c.li |
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Description: 基于FPGA的can 总线设计，采用verilog语言编写。在FPGA的开发环境下，新建一个工程，然后将本文件中的各个源代码添加进工程里，即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run.
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Author: 李浩 |
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Description: 用verilog设计密勒解码器
一、题目：
设计一个密勒解码器电路
二、输入信号：
1． DIN：输入数据
2． CLK：频率为2MHz的方波，占空比为50％
3． RESET：复位信号，低有效
三、输入信号说明：
输入数据为串行改进密勒码，每个码元持续时间为8μs，即16个CLK时钟；数据流是由A、B、C三种信号组成；
A：前8个时钟保持“1”，接着5个时钟变为“0”，最后3个时钟为“1”。
B：在整个码元持续时间内都没有出现“0”，即连续16个时钟保持“1”。
C：前5个时钟保持“0”，后面11个时钟保持“1”。
改进密勒码编码规则如下：
如果码元为逻辑“1”，用A信号表示。
如果码元为逻辑“0”，用B信号表示，但以下两种特例除外：如果出现两个以上连“0”，则从第二个“0”起用C信号表示；如果在“通信起始位”之后第一位就是“0”，则用C信号表示，以下类推；
“通信起始位”，用C信号表示；
“通信结束位”，用“0”及紧随其后的B信号表示。
“无数据”，用连续的B信号表示。-err
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Author: mingming |
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Description: Verilog HDL: Magnitude
For a vector (a,b), the magnitude representation is the following:
A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
-Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
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Author: 郝晋 |
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Description: 倍频详解，IBUFG,BUF,希望大家喜欢-Detailed octave, IBUFG, BUF, hope you like
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Size: 451584 |
Author: 周辉 |
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Description: 除法器的设计本文所采用的除法原理是：对于八位无符号被除数A，先对A转换成高八位是0低八位是A的数C，在时钟脉冲的每个上升沿C 向左移动一位，最后一位补零，同时判断C的高八位是否大于除数B，如是则C的高八位减去B，同时进行移位操作，将C的第二位置1。否则，继续移位操作。经过八个周期后，所得到的C的高八位为余数，第八位为商。从图(1)可清楚地看出此除法器的工作原理。此除法器主要包括比较器、减法器、移位器、控制器等模块。-Divider design used in this paper, the principle of division is: For the eight unsigned dividend A, the first of A into the high-low 8 0 8 is the A number of C, in each clock rising edge to the left C Mobile One, and finally a zero, at the same time to determine whether C is greater than the high-8 divisor B, so is the high C 8 minus B, at the same time shift operation, the location will be C s second one. Otherwise, continue to shift operation. After eight cycles, received a high C for more than eight the number of eighth place for the business. From Figure (1) can clearly see that the divider works. This mainly includes divider comparators, subtraction, and shifter, controller modules.
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Author: lyy |
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Description: 一个QEP电路的verilog代码。输入信号是光电编码器的A相和B相信号和一个处理时钟，输出的是计数信号和方向信号。-A QEP circuit Verilog code. Input signal is the optical encoder of the A phase and B and believe that a deal with the clock, the output is the count signal and direction signal.
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Size: 1024 |
Author: 张洁 |
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Description: 4bit ALU（运算逻辑单元）的设计
给出了此次设计alu的输入输出结构及相应的位数。其中C0是一位的进位输入，A和B分别是4位的数据输入，S0、S1、M分别为一位的功能选择输入信号；Cout是一位的进位输出，F是4为的运算结果输出。-4bit ALU (arithmetic logic unit) design is given in the design of alu input and output structure and the corresponding median. C0 which is a binary input of, A and B are four data entry, S0, S1, M, respectively, as a function of choice of the input signal Cout of a binary output, F is 4 for computing the results of output.
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Author: chenyi |
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Description: verilog code
16-bit carry look-ahead adder
output [15:0] sum // 相加總和
output carryout // 進位
input [15:0] A_in // 輸入A
input [15:0] B_in // 輸入B
input carryin // 第一級進位 C0
-verilog code16-bit carry look-ahead adderoutput [15:0] sum// sum of the aggregate output carryout// binary input [15:0] A_in// input Ainput [15:0] B_in// input Binput carryin// article C0-level binary
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Author: 沙嗲 |
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Description: 采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件.
-FPGA realization of the use of color space conversion RGB to Y CbCr of VHDL and Verilog source code, to support a variety of Xilinx devices.
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Author: Jackson |
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Description: Digital Vlsi Design With Verilog A Textbook From Silicon Valley Technical Institute.pdf
Thisbookisbasedonthelabexercisesandorderofpresentationofacourse
developedandgivenbytheauthoroveraperiodofyearsatSiliconValleyTech-
nicalInstitute,SanJose,California.
Atthetime,totheauthor°Psbestknowledge,thiscoursewastheonlyoneeve
givenwhich(a)presentedtheentireveriloglanguage (b)involvedimplementation
ofafull-duplexserdessimulationmodel or(c)includeddesignofasynthesizable
digitalPLL.
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Author: Frank |
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Description: YUV到RGB的色彩空间转换器(VHDL,Verilog and doc)-Color Space Converter: Y’CrCb to R’G’B’
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Size: 175104 |
Author: wicky |
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Description: this a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corresponding BCD equivalent number by this decoder-this is a verilog code .. it converts 9 bit integer value to its corresponding twelve bit BCD number that is required as an input to a seven segment decoder or otherwise also an integer that may be represented by binary bits can be changed to its corresponding BCD equivalent number by this decoder
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Author: hassan |
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Description: Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File.
The Pinout is descripted in the Constrained file quad.ucf.
To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant.
For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.-Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File.
The Pinout is descripted in the Constrained file quad.ucf.
To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant.
For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.
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Author: JUPP |
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Description: verilog交通灯程式，分别A方向和B方向的交通灯,-verilog of traffic light system,which are A direction and B direction of traffic light.
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Author: llpru |
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Description: 设计可以对两个运动员赛跑计时的秒表:(1）只有时钟（clk）和一个按键（key），每按一次，key是持续一个时钟周期的高电平脉冲
（2）秒表输出用0－59的整数表示
（3）key：
（A）按一下key，开始计数；
（B）第一个运动员到终点时第二下key，记住时间，继续计数；
（C）二个运动员到时按第三下key，停止计数；
（D）然后按第四下key，秒表输出第一个运动员到终点的时间，即按第二下key时记住的计数值；
（E）按第五下key，秒表清0。
-Design of the two athletes running time of the stopwatch: (1) Only the clock (clk) and a button (key), each time, key is continuing a clock cycle, high pulse (2) stopwatch output with 0-59 integer that (3) key: (A) Click the key, start counting (B) When the first player to finish under the second key, remember the time, continue to count (C) two players to press the third Under the key, stop counting (D) and then by the fourth under the key, stopwatch output of the first athletes to the end of the time, that is, the next key by the second count when remembered (E) by the fifth under the key, stopwatch clear 0.
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Author: gab |
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Description: rc5 implementation in verilog for different w/r/b compared with auther code
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Size: 4096 |
Author: rathina |
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Description: 七段数码管译码器.(Verilog)[FPGA]第一个Verilog程序,七段共阴数码管摸索了好几天,终于能完成敲入代码、综合、仿真、绑定引脚至下载的全套工作了 -. 七段数码管的lookup table
module SEG7_LUT (
input [3:0] iDIG,
output reg [6:0] oSEG
)
always@(iDIG)
begin
case(iDIG)
4 h1: oSEG = 7 b1111001 //---t----
4 h2: oSEG = 7 b0100100 // | |
4 h3: oSEG = 7 b0110000 // lt rt
4 h4: oSEG = 7 b0011001 // | |
4 h5: oSEG = 7 b0010010 //---m----
4 h6: oSEG = 7 b0000010 // | |
4 h7: oSEG = 7 b1111000 // lb rb
4 h8: oSEG = 7 b0000000 // | |
4 h9: oSEG = 7 b0011000 //---b----
4 ha: oSEG = 7 b0001000
4 hb: oSEG = 7 b0000011
4 hc: oSEG = 7 b1000110
4 hd: oSEG = 7 b0100001
4 he: oSEG = 7 b0000110
4 hf: oSEG = 7 b0001110
default: oSEG = 7 b1000000
endcase
end
endmodule
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Author: 王林林 |
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Description: beginer level verilog coding
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Size: 1024 |
Author: guy03 |
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