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[VHDL-FPGA-Verilog] QPSK2154

Description: QPSK的VERLOG源码，在MODELSIM下的一个工程，有测试向量。-QPSK VERLOG source of the MODELSIM of a project, test vector.
Platform: | Size: 23552 | Author: 刘仪 | Hits:

[VHDL-FPGA-Verilog] CORDIC01

Description: CORDIC算法的硬件实现 用的verilog语言-CORDIC algorithm Hardware Implementation of the Verilog language
Platform: | Size: 221184 | Author: 李文文 | Hits:

[VHDL-FPGA-Verilog] AM

Description: FPGA内AM调制工程。内带调制波、载波生成。关键词：FPGA verilog AM DDS-AM modulation works within the FPGA. Within the band modulation wave generated carrier. Key words: FPGA verilog AM DDS
Platform: | Size: 1687552 | Author: baixiangzhou | Hits:

[VHDL-FPGA-Verilog] Simulation-and-FPGA-Implementation-of-DigitalDBPSK

Description: 文章介绍了系统的硬件电路原理与具体实现方法，其中主要包括载波恢 复电路，PN 码捕获电路和跟踪电路，并针对Xilinx 公司FPGA 的特点，对各电 路的实现进行优化设计，在不影响系统稳定性和精度的前提下，减少硬件资源 消耗，提高硬件利用率。设计利用Verilog 硬件描述语言完成，通过后仿真验证 电路正确性，并给出综合结果。-This paper introduces the system' s hardware circuit principle and the specific implementation methods, which mainly include the carrier recovery circuit, PN code acquisition circuit and track circuits, and FPGA for Xilinx company characteristics, the implementation of the circuit to optimize the design, without affecting the system stability and precision under the premise of reduced hardware resource consumption, improve hardware utilization. Designed using Verilog Hardware Description Language finish, after the passage of the correctness of circuit simulation, and give General results.
Platform: | Size: 1007616 | Author: mayuan | Hits:

[VHDL-FPGA-Verilog] 16qam——modulation

Description: verilog编写的16qam调制程序，将所有东西装入工程，运行mmm16主程序。其中载波为一个周期采十个点，并乘以2^8-1取整数。在quartusII运行通过。-verilog modulation procedures 16qam prepared all things into works mmm16 to run the main program. One carrier for a cycle of 10 points taken, and multiplied by an integer from 2 ^ 8-1. Running through the quartusII.
Platform: | Size: 5120 | Author: 王力宏 | Hits:

[VHDL-FPGA-Verilog] CFO_Correction

Description: 载波频率同步Verilog程序 基于xilinx ise 实现-Carrier frequency synchronization Verilog program is based on xilinx ise to achieve
Platform: | Size: 412672 | Author: sunk | Hits:

[Other] square_syn

Description: 平方环载波同步法FPGA实现的verilog代码-square loop carrier wave syn
Platform: | Size: 2048 | Author: 白健 | Hits:

[Other] 2psk

Description: 2psk 模块的Verilog实现 （载波为方波）-2psk Verilog module implementation (carrier for the square wave)
Platform: | Size: 3613696 | Author: fqzxw | Hits:

[ELanguage] Miller_encode

Description: 详细介绍了副载波Miller码的编码，采用verilog的编码方式。-Miller introduced the sub-carrier code encoding, the encoding using verilog.
Platform: | Size: 1024 | Author: kevin | Hits:

[Modem program] 16QAM_verilog

Description: 使用Verilog实现全数字的16QAM调制器，假设载波的频率为1MHz，数据比特率为100kbit/s.包括源代码和testbench-use verilog to realize 16qam,carrier frequency is 1MHz,data rate is 100kbit/s.including source code and testbench
Platform: | Size: 749568 | Author: fc | Hits:

[VHDL-FPGA-Verilog] sixiangzaibosheji

Description: 本代码采用Altera公司的FPGA为主控芯片，以开发软件QuartusⅡ为工具。采用EDA设计中的自顶向下与层次式设计方法使用精简的DDS算法完成了输入为14MHz，输出四路频率为70MHz的四相序正弦载波（相位分别为0°、90°、180°、270°）的设计。利用Verilog HDL语言进行了程序设计并用QuartusⅡ对设计进行了仿真，验证了其正确性。-DDS algorithm with simplified input for the completion of 14MHz, 70MHz output frequency of the four four-phase sequence of a sinusoidal carrier (phase were 0 °, 90 °, 180 °, 270 °) design. Using Verilog HDL language for the programming and design with the Quartus Ⅱ of the simulation to verify its correctness.
Platform: | Size: 5120 | Author: biyuming | Hits:

[VHDL-FPGA-Verilog] costas

Description: 载波同步，costas环，基于Verilog的载波同步环-Carrier synchronization, costas ring, based on Verilog carrier synchronization ring
Platform: | Size: 5120 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] ppt

Description: 1、可编程逻辑器件，即应用EDA技术完成电子系统设计的载体； 2、硬件描述语言（VHDL 或者 Verilog）。它用来描述系统的结构和功 能，是EDA的主要表达手段； 3、配套的软件工具。它用来完成电子系统的智能化设计； 4、实验开发系统。在整个EDA设计电子系统的过程中，实验开发系统是实现可编程器件下载和验证的工具， -A programmable logic device, the application of EDA technology to complete the carrier of the electronic system design 2, the hardware description language (VHDL or Verilog). It is used to describe the structure and function of the system, is the main means of expression of the EDA 3, and the supporting software tools. It is used to complete the intelligent design of electronic systems experimental development system. In the process of the entire EDA design of electronic systems, experimental development system is a tool to download and verification of programmable devices.
Platform: | Size: 13585408 | Author: 周爱丹 | Hits:

[GPS develop] Code_NCO.zip

Description: 码数控振荡器相位累加器的位数N为32,利用verilog HDL语言在Quartus II 9.1中具体实现了载波和码NCO的设计。,The code numerically controlled oscillator phase accumulator bits N 32 verilog HDL language in the concrete realization of the design of the carrier and code NCO Quartus II 9.1.
Platform: | Size: 1024 | Author: cc | Hits:

[source in ebook] Pilot_Insert

Description: 导频插入，此程序用ISE的verilog编写，主要用于载波提取和采样频率同步-Pilot insertion procedures prepared by the ISE verilog, mainly used for carrier extraction and sampling frequency synchronization
Platform: | Size: 161792 | Author: 牧童 | Hits:

[VHDL-FPGA-Verilog] up_down_counter

Description: the code is written by verilog HDL, and present a kind of up-down counter to realize triangle carrier
Platform: | Size: 428032 | Author: 宫杰 | Hits:

[VHDL-FPGA-Verilog] QPSK_DSSS

Description: 该程序使用verilog语言，编写了QPSK-DSSS系统的发端，主要模块包括对同相分量和正交分量的扩频，通过根升余弦滤波器，以及与载波相乘等模块。-The program uses the verilog language, written QPSK-DSSS system, the originator, the main modules include in-phase and quadrature components of the spectrum, through the root raised cosine filter, as well as with carrier multiplication modules.
Platform: | Size: 6983680 | Author: 林源 | Hits:

[VHDL-FPGA-Verilog] syn

Description: 载波同步的verilog代码，是新手学习同步的最佳选择，值得推荐。-Verilog code carrier synchronization, synchronization is the best choice for novices to learn, it is worth recommending.
Platform: | Size: 158720 | Author: 晨雾 | Hits:

[Documents] 三角函数的Verilog HDL语言实现

Description: 以Actel FPGA作为控制核心，通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波，利用Verilog HDL语言实现死区时间可调的SPWM全数字算法，并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, realize the adjustable dead time using Verilog HDL language of the SPWM digital algorithm and digital SPWM algorithm is realized in Fushion StartKit development board.)
Platform: | Size: 148480 | Author: 所罗门 | Hits:

[Com Port] d974d4330bf7

Description: 这是一个非常完整的qpsk调制解调用fpga实现的工程，在工程中已经能够正常使用，使用的quartus ii 开发，使用Verilog语言，文件中还包含了各种滤波器的系数文件，还有matlab仿真文件，整个工程包含从串并变换，相位映射，到成型滤波，中通滤波，cic滤波，调制，再到解调过成的下变频，匹配滤波，载波提取，位定时，判决，整个完整的过程(This is a very complete QPSK modulation and demodulation using FPGA implementation of the project, the project has been able to properly use the Quartus II development, the use of Verilog language, the file also contains the files of various filter coefficients, and MATLAB simulation files, including the entire project from the string and transform, phase mapping, molding in filtering, filtering, CIC filtering, modulation, and demodulation frequency, a matched filter, carrier extraction, timing, judgment, the whole course)
Platform: | Size: 13488128 | Author: maerzaizai | Hits:
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