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[VHDL-FPGA-Verilog] cic_4_dec

Description: 实现4倍抽取的CIC抽取滤波器模块的Verilog实现，在对数据进行抽取之前，首先进行滤波-Extracted 4 times realize CIC decimation filter module Verilog realize that in the data collected before the first filter
Platform: | Size: 1024 | Author: 楚鹤 | Hits:

[Books] fir

Description: 本文以软件无线电为指导，提出基于CORDIC算法利用FPGA平台数字下变频器设计方案。首先分析下变频器的结构；然后采用模块化设计思想，将数字下变 频的功能模块包括数字控制振荡器、CIC抽取滤波、HBF抽取滤波器、FIR低通滤波器进行分析和FPGA的设计；最后在 MATLAB/DSPBuilder下硬件仿真模块进行仿真并给出仿真结果。-In this paper, software-defined radio as the guidance, based on the CORDIC algorithm uses the FPGA platform, digital down-converter design. First analyzes the structure of down-converter and then use a modular design concept, the digital down-conversion function modules including digital controlled oscillator, CIC decimation filtering, HBF decimation filter, FIR low-pass filter for analysis and FPGA design the final In the MATLAB/DSPBuilder under the hardware emulation module simulation and simulation results.
Platform: | Size: 201728 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] cic_dec_8_five

Description: CIC抽取滤波器，抽取系数8,verilog版本，用于数字下变频-CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion
Platform: | Size: 1024 | Author: 王刚 | Hits:

[VHDL-FPGA-Verilog] cic

Description: 抽取滤波的Verilog实现，经测试可用-Decimation filter
Platform: | Size: 1024 | Author: anderson | Hits:

[VHDL-FPGA-Verilog] cic-1

Description: cic滤波器2倍抽取verilog代码及testch-cic filter decimation verilog code and testch
Platform: | Size: 2048 | Author: 黄远望 | Hits:

[Other] cic_dec_8_three

Description: 用verilog语言实现一个3级、抽取率为2的8位hogenauer CIC抽取滤波器-Verilog language to achieve a 3, the extraction rate of 8 hogenauer CIC decimation filter
Platform: | Size: 1024 | Author: 刘冰瑶 | Hits:

[VHDL-FPGA-Verilog] 24CIC

Description: 基于fpga的抽取CIC滤波器设计,采用verilog编写，24抽取,仿真通过-Fpga-based CIC decimation filter design using verilog written, 24 extraction
Platform: | Size: 3638272 | Author: zengdeqian | Hits:

[VHDL-FPGA-Verilog] cic_cq

Description: 在altera平台用verilog硬件描述语言实现cic抽取滤波，包含完整的工程代码，已经仿真通过，可以直接用于实践-In the Altera platform using Verilog hardware description language CIC decimation filter, contains the complete project code, has been adopted by simulation, can be used directly in practice
Platform: | Size: 1182720 | Author: 汪少锋 | Hits:

[Other] cic

Description: CIC Filter 实现的matlab源码.里面使用MATLAB，verilog，c++混合实现CIC抽取滤波器-CIC Filter achieve matlab source. Inside using MATLAB, verilog, c++ hybrid implementation CIC decimation filter
Platform: | Size: 290816 | Author: 李瑞涛 | Hits:

[VHDL-FPGA-Verilog] CIC_verilog

Description: 采用verilog实现的三级CIC抽取器，输入8位数据，输出26位数据，使用有限状态机用于实现下采样，包括积分器实现模块和梳状器实现模块-Using verilog to achieve three CIC decimation filter, the input 8-bit data output 26-bit data, the use of finite state machines for sampling, including the integrator and comb to implement the module is implemented to achieve the next module
Platform: | Size: 1024 | Author: 刘建涛 | Hits:

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