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[VHDL-FPGA-Verilog] Clock_generator

Description: Verilog source code for a clock generator
Platform: | Size: 1024 | Author: austin | Hits:

[VHDL-FPGA-Verilog] clock_generator

Description: clock generator verilog代码，供大家参考-clock generator verilog code for your reference
Platform: | Size: 163840 | Author: 袁科学 | Hits:

[VHDL-FPGA-Verilog] sequencecontroller

Description: this is source code in verilog for sequence controller and clock generator which is used in RISC cpu
Platform: | Size: 99328 | Author: Harshit B J | Hits:

[VHDL-FPGA-Verilog] 5B6B-codec

Description: verilog hdl实现5B6B编译码（光纤通信线路码型），包含了时钟发生器模块 ，信号源模块 ，编码模块 ，译码模块， 和检错模块，并通过modesim仿真验证。-verilog hdl achieve 5B6B encoding and decoding (code-based fiber-optic communication lines), contains a clock generator module, signal source modules, code modules, decoding module, and error detection module, and through modesim simulation.
Platform: | Size: 4096 | Author: 林海全 | Hits:

[VHDL-FPGA-Verilog] VeriRISC_CPU_Verilog

Description: Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clock generator. Testbench is included.
Platform: | Size: 9216 | Author: 张昊溢 | Hits:

[Other Embeded program] CLOCK_GENERATOR

Description: 一个verilog时钟发生器源代码，能够满足最小时间间隔0.1ns的时钟计时要求。-A clock generator verilog source code, to meet the minimum time interval of 0.1ns clock timing requirements.
Platform: | Size: 1024 | Author: 孙斌 | Hits:

[VHDL-FPGA-Verilog] clock

Description: Clock generator code in Verilog for Stop Watch
Platform: | Size: 1024 | Author: Uzair | Hits:

[VHDL-FPGA-Verilog] time60

Description: 一个占用资源很少的时钟产生Verilog代码，值得借鉴-A small footprint clock generator Verilog code, is worth learning
Platform: | Size: 1024 | Author: wangzao | Hits:

[VHDL-FPGA-Verilog] ClockGenerator

Description: Verilog code for a programmable clock generator
Platform: | Size: 963584 | Author: tom | Hits:

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