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[Embeded-SCM Develop] lzma

Description: lzma的压缩算法再嵌入式系统上的实现，lzma是一个对bin类型文件压缩比很高的压缩算法，一般压缩后的文件大小是原理的1/3-LZMA compression algorithm embedded system again on the realization LZMA was a bin file types high compression ratio of compression algorithm, the general compressed file size is the principle of 1/3
Platform: | Size: 7168 | Author: 木头 | Hits:

[VHDL-FPGA-Verilog] alu

Description: verilog编写的alu模块-Verilog modules prepared by the ALU
Platform: | Size: 1024 | Author: 刘陆陆 | Hits:

[VHDL-FPGA-Verilog] LCD1602

Description: LCD1602显示源代码 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是标准的16×2字符型液晶模块上显示字符串； 3-LCD1602 display the source code 1. Source file stored in the src directory, QII the project file stored in the directory Proj 2. Realize the function of the procedure is a standard 16 × 2 character LCD module to display the string 3
Platform: | Size: 716800 | Author: 张海风 | Hits:

[VHDL-FPGA-Verilog] trueif

Description: 一个超前进位加法器（及其testbench) .v文件-A CLA (and its testbench). V file
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个桶形移位寄存器的.v文件，含testbench-Shift Registers a bucket. V file containing Testbench
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个简单状态机的.v文件，含testbench-A simple state machine. V file containing Testbench
Platform: | Size: 1024 | Author: QU YIFAN | Hits:

[VHDL-FPGA-Verilog] crc16_ccitt

Description: crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module. -crc_table.c is for reset seed (0000) crc_table_1.c is for reset seed (ffff) CRC16_D8_m.v is a verilog module of byte paralle crc.CRC16_D8_m_tb.v is the testbench file of above module.
Platform: | Size: 3072 | Author: 樊文杰 | Hits:

[VHDL-FPGA-Verilog] uart(Verilog)

Description: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
Platform: | Size: 10240 | Author: 阿军 | Hits:

[Other] CLOCK_co-design_of_C_and_Verilog

Description: A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
Platform: | Size: 37888 | Author: Annbb | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL

Description: 《Verilog-HDL实践与应用系统设计》一书中的光盘源文件- Verilog-HDL practice and application of system design, a book on CD-ROM source file
Platform: | Size: 771072 | Author: 范田田 | Hits:

[VHDL-FPGA-Verilog] adder4

Description: 是用verilog写得加法器以及计数器里面有测试文件（testbench），对于初学者来说这个可以用来参考下-Is written in Verilog adder and counter inside a test file (testbench), for beginners this can be used to reference the next
Platform: | Size: 1024 | Author: olive | Hits:

[VHDL-FPGA-Verilog] uart

Description: This Verilog file is a desription of an UART, which is a piece of computer hardware that translates data between parallel and serial forms.
Platform: | Size: 1024 | Author: Balazs Jozsa | Hits:

[Com Port] UART

Description: 利用Verilog实现一个UART接口，包含三个源文件rcvr.v\txmit.v\uart.v -Verilog realization of the use of a UART interface, the source file contains three rcvr.v \ txmit.v \ uart.v
Platform: | Size: 2048 | Author: speed | Hits:

[VHDL-FPGA-Verilog] IIRtest

Description: quartusII9.0开发环境下巴特沃斯IIR滤波器的实现完整的工程文件，同时里面有文档详细说明如何用modelsim对altera芯片进行仿真-development environment quartusII9.0 Butterworth IIR filter to achieve a complete project file, but there are documents in detail how to use modelsim to altera-chip simulation
Platform: | Size: 44793856 | Author: 赵辉 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: FPGA控制AD9854的源文件，verilog，附有简单文档。-FPGA to control the AD9854 source file, verilog, with a simple document.
Platform: | Size: 820224 | Author: 柴佳 | Hits:

[VHDL-FPGA-Verilog] Decoder

Description: This a verilog file which is used as a decoder-This is a verilog file which is used as a decoder
Platform: | Size: 100352 | Author: hungnguyen | Hits:

[Algorithm] cordic_atan

Description: 用verilog语言实现计算反正切函数，在软件无线电中解调PM/FM中使用的尤为频繁。上传的压缩包是modelsim工程，基于6.5c,里边包含一个完整的PM波产生以及解调过程的matlab文件仿真，并取其中间的I和Q支路做为verilog文件的输入，并将其借条输出与MATLAB实际解调输出作比较。 鉴相器的设计基于CORDIC算法，其精度取决于迭代的深度。由于工程实际运用只需要解调出atan值，并不需要绝对的值，所以并没有给予加权，需要的同学可以自己加上。-Calculated using verilog language arc tangent function, the software radio demodulation PM/FM is particularly used frequently. From the archive is modelsim project, based on 6.5c, inside the PM contains a complete demodulation process of wave generation and simulation matlab file, and whichever is the middle of the I and Q branch verilog file as input, and its IOU demodulated output and actual output of MATLAB for comparison. Phase detector design is based on CORDIC algorithm, its accuracy depends on the iteration depth. As the practical application of engineering demodulated atan value only and does not need absolute value, and there is no weight given to the need of the students can add their own.
Platform: | Size: 79872 | Author: Jorge | Hits:

[VHDL-FPGA-Verilog] verilog-PS2-Keyboard

Description: veirlog编写的PS2键盘通讯程序, 并有PS2接口的相关说明, Quartus II 8.1工程文件-veirlog written communication procedures PS2 keyboard, and a PS2 interface instructions, Quartus II 8.1 project file
Platform: | Size: 512000 | Author: Joseph | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[VHDL-FPGA-Verilog] Verilog HDL program

Description: 文件详细讲述了使用XILINX产FPGA在ISE平台开发的方法，介绍了Modelsim，chipscope,textbench等仿真方法，并含大量实例以及源代码(File details on the use of XILINX produced FPGA in the ISE platform development methods, introduced the Modelsim, chipscope, textbench and other simulation methods, and contains a large number of examples, as well as source code)
Platform: | Size: 11567104 | Author: 没伞的孩子 | Hits:
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