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[Home Personal application] digtalclk

Description: 用Altera公司的QuartusII编写的电子钟程序，可以下载至开发板，实现一个智能数字钟功能，计时，校时，闹钟，跑表等功能，也可用于学习verilog HDL语言与数字逻辑-Using Altera s QuartusII procedures for the preparation of electronic bell, you can download to a development board, the realization of an intelligent digital clock function, time, school time, alarm clock, stopwatch functions can also be used to study verilog HDL language and digital logic
Platform: | Size: 2094080 | Author: 张欢 | Hits:

[VHDL-FPGA-Verilog] digital_clock

Description: 用veriolg写的数字钟实验，具有定点报时，闰年判断，年月日显示，下载平台为spantan3s400。有详细注解。适合verilog学习-Written by veriolg digital clock experiments with fixed time, to determine leap year, date display, download platform spantan3s400. Have a detailed annotation. Suitable for learning Verilog
Platform: | Size: 1186816 | Author: 屠宁杰 | Hits:

[VHDL-FPGA-Verilog] clock_design

Description: 数字钟的verilog代码，quartusII开发环境.-Digital Clock in Verilog code, quartusII development environment.
Platform: | Size: 414720 | Author: 屈开 | Hits:

[SCM] clock

Description: 一个用verilog编写的数字时钟，最后在8段数码管上显示出来，对于初学verilog的有一定的帮助，是一个工程文件-Verilog prepared using a digital clock, the last paragraph in 8 out digital tube display, for the novice Verilog have some help, is a project file
Platform: | Size: 603136 | Author: wphyl | Hits:

[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga

Description: 基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Platform: | Size: 3293184 | Author: | Hits:

[VHDL-FPGA-Verilog] multifunction_clock

Description: 此为多功能数字电子钟的vhdl代码，有闹钟、时间可调、计时等功能-This is a multi-function digital electronic clock VHDL code, has an alarm clock, time adjustable, timing and other functions
Platform: | Size: 4096 | Author: naturexu | Hits:

[VHDL-FPGA-Verilog] shuzizhong

Description: 设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。 实验平台： 1. 一台PC机； 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
Platform: | Size: 425984 | Author: 盼盼 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: dpll的verilog代码，完成数字锁相。用于时钟对准，位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization.
Platform: | Size: 1024 | Author: hsj | Hits:

[Windows Develop] verilog_clock_time

Description: 用verilog编写的多功能数字钟,非常适合那些需要这方面开发的人员。-Prepared using verilog multifunction digital clock, ideally suited for the development of personnel in this regard.
Platform: | Size: 5120 | Author: lilei | Hits:

[VHDL-FPGA-Verilog] clock

Description: 多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
Platform: | Size: 984064 | Author: Stone Lei | Hits:

[VHDL-FPGA-Verilog] digital-clock

Description: 该程序是有verilog实现的fpga的交通灯 适用于cycloneII芯片 可供fpga初学者学习verilog语言时参考，不仅可以显示时钟 还能调整时钟分针秒针-The program is a verilog realize fpga of traffic light is applicable to cycloneII chips available for beginners to learn verilog fpga languages as reference, not only can display the clock can adjust clock minute hand a second hand
Platform: | Size: 589824 | Author: 林原 | Hits:

[Mathimatics-Numerical algorithms] clock

Description: Verilog 编写的60进制的计数器，可以用来设计数字钟、频率计等-count_60 for digital clock using Verilog
Platform: | Size: 1024 | Author: 刘胜 | Hits:

[Internet-Network] digital_watch_lcd_core

Description: a verilog code for digital clock
Platform: | Size: 1024 | Author: abdul | Hits:

[ELanguage] dIGITAL-CLOCK

Description: Verilog code for digital clock
Platform: | Size: 2048 | Author: nisal senarathne | Hits:

[Software Engineering] Verilog-Code-For-Digital-Clock-Project

Description: Verilog code for digital clock project
Platform: | Size: 10240 | Author: farida banu | Hits:

[Other] Verilog-135-classic-design

Description: verilog的135个经典设计，适合初学者自学。内有FIR、数字钟、交通灯、串转并、ram、rom等等常用模块的完整verilog代码，以及测试程序。还有基本的设计源码-verilog of 135 classic design, suitable for beginners learning. There are FIR, complete verilog code for a digital clock, traffic lights, and turn string, ram, rom, etc. commonly used modules, and test procedures. There are basic design source
Platform: | Size: 116736 | Author: 王凌 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 多功能数字钟的verilog程序，可用于年月日的记时和显示。-Multi-function digital clock verilog procedures, can be used for date time and display.
Platform: | Size: 390144 | Author: 万力 | Hits:

[VHDL-FPGA-Verilog] Digital_Clock

Description: 用verilog写的数字时钟代码，亲测可用，可自行编写test bench进行仿真(Written in Verilog digital clock code, pro test available, you can write your own test bench for simulation)
Platform: | Size: 2048 | Author: 一寸光阴 | Hits:

[VHDL-FPGA-Verilog] Clock

Description: 本设计实现了一种基于FPGA的数字时钟设计，应用Verilog硬件描述语言进行数字电路设计，采用自顶向下的方法将电路系统逐层分解细化，设计数字时钟总体结构、各模块及相应具体电路。在Quartus II 9.0工具软件环境下编译、仿真。最后下载到FPGA实验平台进行测试。本数字时钟具有显示时间、通过按键校准时间、整点报时等功能。(This design realizes a digital clock design based on FPGA, uses the Verilog hardware description language to design the digital circuit, uses the top down method to decompose the circuit system layer by layer, and designs the overall structure of the digital clock, each module and the corresponding specific circuit. Compile and simulate in Quartus II 9 tool software environment. Finally downloaded to the FPGA experimental platform for testing. This digital clock has the functions of display time, calibration time through keys, timing of whole points and so on.)
Platform: | Size: 3836928 | Author: 威威谈谈 | Hits:

[VHDL-FPGA-Verilog] clock

Description: FPGA编程，用Verilog语言实现数字钟功能(The FPGA programming, the function for digital clock with Verilog language)
Platform: | Size: 1176576 | Author: 龚俊 | Hits:
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