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[Other resource] FPGApro

Description: VERILOG HDL 实际工控项目源码 开发工具 altera quartus2-verilog HDL actual industrial projects source development tools altera quartus2
Platform: | Size: 1229312 | Author: zc | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram控制器 这里考虑将SDRAM控制器结合目前项目开展来做相应的模块，而不做SDRAM通用控制器，这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单，没有多余的逻辑资源有利于提高控制器的速度，满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, as well as consider the FPGA device resources and the measures taken. While the preparation of simple logic, the logic is no spare resources to improve the speed controller to meet the final design requirements.
Platform: | Size: 3072 | Author: 林博 | Hits:

[VHDL-FPGA-Verilog] dll11254

Description: 数字琐相环DPLL的VERLOG代码，MODELSIM下的工程，有测试文件-digital phase-locked loop DPLL VERLOG code MODELSIM under the projects, a test document
Platform: | Size: 19456 | Author: 刘仪 | Hits:

[Other] 2005_LinuxKernelDevelopment[2ED]_RobertLove

Description: The Linux kernel is one of the most interesting yet least understood open-source projects. It is also a basis for developing new kernel code. That is why Sams is excited to bring you the latest Linux kernel development information from a Novell insider in the second edition of Linux Kernel Development. This authoritative, practical guide will help you better understand the Linux kernel through updated coverage of all the major subsystems, new features associated with Linux 2.6 kernel and insider information on not-yet-released developments. You ll be able to take an in-depth look at Linux kernel from both a theoretical and an applied perspective as you cover a wide range of topics, including algorithms, system call interface, paging strategies and kernel synchronization. Get the top information right from the source in Linux Kernel Development. -The Linux kernel is one of the most interest ing yet least understood open-source projects . It is also a basis for developing new kernel cod e. That is why Sams is excited to bring you the lat est Linux kernel development information from a Novell insider in the second edition of Linux K ernel Development. This authoritative. practical guide will help you better understan d the Linux kernel through updated coverage of a ll the major subsystems, new features associated with a Linux 2.6 kernel nd insider information on not-yet-released de velopments. You'll be able to take an in-depth lo ok at Linux kernel from both a theoretical and an applied perspective as you cover a wide range of topics, including algorithms, system call interface. paging strategies and kernel synchronization . Get
Platform: | Size: 1334272 | Author: 李中伟 | Hits:

[VHDL-FPGA-Verilog] div

Description: div的verilog开发程序，做稍微修改就可以应用到具体的工程当中-div of Verilog development process, make a slight modification can be applied to specific projects which
Platform: | Size: 167936 | Author: 杨华 | Hits:

[VHDL-FPGA-Verilog] 16550

Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.
Platform: | Size: 10240 | Author: David.Mr.Liu | Hits:

[VHDL-FPGA-Verilog] tft_cntlr_ref_v1_00_c

Description: TFT LCD 控制器的VERILOG 源代码程序,已在某项目上成功应用.-TFT LCD controller VERILOG source code procedures have been in a successful application projects.
Platform: | Size: 15360 | Author: liubing | Hits:

[VHDL-FPGA-Verilog] FIFO_Buffer

Description: Verilog的FIFO源代码，可综合，并以运用到具体工程中-Verilog source code of the FIFO can be integrated and applied to specific projects
Platform: | Size: 1024 | Author: david | Hits:

[VHDL-FPGA-Verilog] i2c_ip

Description: I2C的ip核，Verilog实现，可以直接用在你的项目中。I2C是一种简单实用的通讯协议。-I2C' s ip nuclear, Verilog realization, you can directly use in your projects. I2C is a simple and practical protocol.
Platform: | Size: 2207744 | Author: caibaiyin | Hits:

[Embeded-SCM Develop] verilogprojects

Description: file is about verilog projects
Platform: | Size: 22462464 | Author: sant | Hits:

[VHDL-FPGA-Verilog] 8051core-Verilog

Description: 利用VerilogHDL语言，编程实现8051单片机的功能，在FPGA的工程中有广泛的应用-Use VerilogHDL language programming 8051 microcontroller functions in FPGA projects in a wide range of applications
Platform: | Size: 52224 | Author: luosheng | Hits:

[VHDL-FPGA-Verilog] rs232

Description: 本设计是PC和FPGA的串口通信的程序，用的是VERILOG语言，调试成功，用户可根据自己的项目稍作改动。-The design is a PC and the FPGA' s serial communication procedures, using a VERILOG language, debugged, the user can make a little change according to their own projects.
Platform: | Size: 2048 | Author: 陆景鹏 | Hits:

[VHDL-FPGA-Verilog] 5-ge-ram-core

Description: 5个ram核，arm6_verilog,arm7_verilog_1,arm7_VHDL,Core_arm_VHDL,nnARM01_11_1_3 arm6_verilog.rar 一个最简单的arm内核，verilog写的，有点乱 arm7_verilog_1.rar J. Shin用verilog写的arm7核心，结构良好，简明易懂 nnARM01_11_1_3.zip.zip nnARM开源项目，国防科技大学牛人ShengYu Shen写的，原来放在opencores上，因为写得太好了，后被ARM公司封杀~~这里是目前我能找到的最终版本了~ Core_arm_VHDL.rar VHDL语言实现的arm内核，可以在http://www.opencores.org/project,core_arm下载到，不过还不是非常完整，有些小bug ARM7_VHDL.rar Ruslan Lepetenok用VHDL写的arm内核，也非常不错-5 ram nuclear, arm6_verilog, arm7_verilog_1, arm7_VHDL, Core_arm_VHDL, nnARM01_11_1_3 arm6_verilog.rar arm of a simple kernel, verilog to write, a bit messy arm7_verilog_1.rar J. Shin arm7 use verilog to write the core of well-structured, easily understandable nnARM01_11_1_3 . zip.zip nnARM open source projects, National Defense University cattle ShengYu Shen wrote, the original on the opencores, because so good, and after the ban, ARM ~ ~ Here is the final version I could find out ~ Core_arm_VHDL.rar VHDL language of the arm core, you can http://www.opencores.org/project, core_arm downloaded to, but not very complete, and some small bug ARM7_VHDL.rar Ruslan Lepetenok written in arm with VHDL core, but also very good
Platform: | Size: 1152000 | Author: YeZiqiang | Hits:

[VHDL-FPGA-Verilog] waveform

Description: Verilog HDL数字系统设计项目，频率可调的任意波形发生器，可以输出正弦波、方波、三角波和反三角四种波形-Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform
Platform: | Size: 2274304 | Author: saln | Hits:

[VHDL-FPGA-Verilog] FPGA-verilog

Description: FPGA一些小工程的verilog源程序，对初学者还是比较有帮助的。-FPGA some small projects of the Verilog source code, for beginners or more help.
Platform: | Size: 7391232 | Author: 李镇江 | Hits:

[VHDL-FPGA-Verilog] JTAG_Example0_Verilog

Description: 一个Verilog的JTAG程序例子，包括完整的说明文档和源文件。(tap_top.v This file is part of the JTAG Test Access Port (TAP) http://www.opencores.org/projects/jtag/ Author(s): Igor Mohor (igorm@opencores.org))
Platform: | Size: 386048 | Author: ZhouGuofei | Hits:

[VHDL-FPGA-Verilog] BIC

Description: this project for adaptive schme techniques by using LFSR design projects
Platform: | Size: 175104 | Author: king of VLSI | Hits:

[VHDL-FPGA-Verilog] FPGA-Projects-master

Description: FPGA BASYS3 PROJECTS
Platform: | Size: 55296 | Author: prasannasaragada | Hits:

[VHDL-FPGA-Verilog] 单周期CPU大作业-2020

Description: Verilog projects cpu
Platform: | Size: 889856 | Author: sast | Hits:

[VHDL-FPGA-Verilog] AM调制解调

Description: 基于Artix-7 FPGA的AM调制解调代码，从AD读入信号后，进行AM调制，并解调输出（将代码分成两个工程就是AM的调制和解调），其中解调用到的数字滤波采用MATLAB设计(The AM modulation and demodulation code based on artix-7 FPGA, after reading the signal from AD, carries out AM modulation, and demodulates the output (the code is divided into two projects, namely AM modulation and demodulation). The digital filter used in demodulation is designed by MATLAB)
Platform: | Size: 41027584 | Author: Emmanuel000 | Hits:
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