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[VHDL-FPGA-Verilog] clock

Description: verilog program for real time clock.. select the .v file to view the code.
Platform: | Size: 220160 | Author: Arjun | Hits:

[Other] RTC

Description: verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等-verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other
Platform: | Size: 12288 | Author: 郭晓进 | Hits:

[VHDL-FPGA-Verilog] verilog_code

Description: Verilog code for Traffic Light Controller, Real Time Clock
Platform: | Size: 15360 | Author: Vinodh | Hits:

[Other] sss

Description: 基于verilog语言的DS1302实时时钟驱动-DS1302 real-time clock driver based on Verilog language
Platform: | Size: 1024 | Author: 王玲 | Hits:

[VHDL-FPGA-Verilog] bluespec-h264_latest.tar

Description: H.264硬件视频解码，采用verilog代码设计，支持1.5M时钟下30bps的QCIF分辨率的实时视频解码-H. 264 hardware video decoder, use verilog code design, support under 1.5 M clock 30 BPS QCIF resolution of real-time video decoding
Platform: | Size: 16858112 | Author: YUKAI ZHANG | Hits:

[VHDL-FPGA-Verilog] LTC_1867_driver

Description: Verilog实现LTC1867的驱动程序，功能：四路单端输入CH0~CH3，系统时钟频率50MHZ，SCK为12.5MHZ，接收数据按通道四路实时输出，输出频率为100HZ，16位数据。-Verilog realize LTC1867 driver features: four single-ended input CH0 ~ CH3, the system clock frequency is 50MHZ, SCK is 12.5MHZ, receive data by channel four real-time output, the output frequency is 100HZ, 16-bit data.
Platform: | Size: 3067904 | Author: 陈勇 | Hits:

[VHDL-FPGA-Verilog] RTC

Description: Verilog语言编写的IIC读取RTC实时时钟程序(real time clock based on FPGA)
Platform: | Size: 2080768 | Author: 紫帝 | Hits:

[VHDL-FPGA-Verilog] FPGA_实时时钟设计

Description: 通过配置DS1302芯片来实现实时时钟的监测，我们通过通过控制2个按键来选择我们要在数码管上显示的时间，按下按键1我们来显示周几，按下按键2来显示年月日，不按显示时分秒，这样显示复合我们的数字表的显示(By configuring DS1302 chip to monitor the real-time clock, we select the time that we want to display on the digital tube by controlling 2 keys. Press key 1 to show the week, press the key 2 to show the year and month, not according to the display time, so that the display of the display of the display of our digital table.)
Platform: | Size: 356352 | Author: 硅渣渣 | Hits:

[VHDL-FPGA-Verilog] 现有16位寄存器。初始值为0

Description: 现有16位寄存器。初始值为0。每个时钟周期寄存器的值会左移1位，并且将输入的数据data_in作为寄存器的最低位，寄存器原来的最高位将被丢弃。要求每个周期实时输出该16位寄存器对7求余的余数data_out[20]。(Existing 16 bit register. The initial value is 0. The value of each clock cycle register will shift 1 bit to the left, and the input data will be_ In as the lowest bit of the register, the original highest bit of the register will be discarded. It is required to output the remainder data of the 16 bit register to 7 in real-time in each cycle_ out[20].)
Platform: | Size: 457728 | Author: echokiii | Hits:

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