Search - verilog risc

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[Embeded-SCM Develop] freerisc8_11 DL : 0: 8位RISC　CPU的VERILOG编程　SOURCECODE-8 RISC CPU VERILOG programs SOURCECODE
Update : 2025-02-17 Size : 269kb Publisher : zfhustb
[Applications] RISC Core_verilog DL : 0: RISC的指令VerilogHDL实现-RISC instructions to achieve VerilogHDL
Update : 2025-02-17 Size : 131kb Publisher : 王晓东
[Other] cpu的VERILOG描述 DL : 0: RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL description
Update : 2025-02-17 Size : 361kb Publisher : 陈俊
[ARM-PowerPC-ColdFire-MIPS] embedded_risc DL : 0: 一个嵌入式RISC CPU 的Verilog 设计源码，可综合。内含详细的设计文挡。-an embedded RISC CPU design Verilog source code can be integrated. Detailed design containing the text block.
Update : 2025-02-17 Size : 125kb Publisher : 箫勇天
[VHDL-FPGA-Verilog] RISC DL : 0: hrisc cpu，为何只有vhdl选择呢？大家都用verilog的啊-hrisc cpu why only VHDL choice? We all use the Verilog ah
Update : 2025-02-17 Size : 125kb Publisher : 12
[Algorithm] riscdesign DL : 0: 一个非常简单的cpu设计的原代码,是用verilog编写的-a very simple cpu design of the original code, was prepared by the Verilog
Update : 2025-02-17 Size : 713kb Publisher : wanglei
[VHDL-FPGA-Verilog] riscpu DL : 1: 一个32位微处理器的verilog实现源代脉,采用5级流水线和cache技术.-a 32 Microprocessor verilog achieve pulse generation sources, used five lines and cache technology.
Update : 2025-02-17 Size : 149kb Publisher : 大为
[ARM-PowerPC-ColdFire-MIPS] risc_8051_v DL : 0: 流片过的risc_8051源代码 verilog语言描述的~-flow unit off risc_8051 verilog language source code described in the ~
Update : 2025-02-17 Size : 36kb Publisher : 李明纬
[ARM-PowerPC-ColdFire-MIPS] cpu DL : 0: 精简指令cpu，用verilog编写，详细的教程-RISC cpu, using Verilog prepared and detailed tutorial
Update : 2025-02-17 Size : 210kb Publisher : 郑欲
[SCM] 32-bit_RISC_IP_Core DL : 0: 32位RISC单片机verilog源码内包含说明文档经过他人测试通过-32-bit RISC single-chip Verilog source code contains documentation of others after the test
Update : 2025-02-17 Size : 33kb Publisher : 栾日超
[VHDL-FPGA-Verilog] RiscCPU8 DL : 0: 可综合的VerilogHDL设计实例: ---简化的RISC 8位CPU设计简介--- -VerilogHDL be integrated design example:--- simplified RISC 8 bit CPU design Introduction---
Update : 2025-02-17 Size : 214kb Publisher : hulin
[Other] RiscCpu DL : 1: Verilog-RISC CPU 代码实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware description language, and design methods. The procedure adopted ModelSim simulation. BUAA
Update : 2025-02-17 Size : 9kb Publisher : sss
[ARM-PowerPC-ColdFire-MIPS] risc DL : 0: 嵌入式risc处理器源码，包含设计文档，原理图，testbench，及外围接口，使用verilog实现。-Source embedded RISC processors, including design documents, schematics, testbench, and peripheral interfaces, the use of Verilog to achieve.
Update : 2025-02-17 Size : 126kb Publisher : 李林
[VHDL-FPGA-Verilog] RISC8.ZIP DL : 0: verilog RISC8 cpu CORE 8位RISC CPU 内核源码（VERILOG 版）-verilogRISC8 cpu CORE8-bit RISC CPU core source (VERILOG version)
Update : 2025-02-17 Size : 79kb Publisher : likui
[Other] risc DL : 0: 基于quartus II软件用verilog 语言描述的精简指令CPU-quartus II verilog
Update : 2025-02-17 Size : 1.2mb Publisher : xu
[VHDL-FPGA-Verilog] risc DL : 0: 用Verilog 编写的8位risc cpu，行为级描述，可综合-6 bits risc cpu by Verilog
Update : 2025-02-17 Size : 129kb Publisher : 徐明
[VHDL-FPGA-Verilog] soc-gr0040-010309 DL : 0: xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
Update : 2025-02-17 Size : 397kb Publisher : urga turg
[VHDL-FPGA-Verilog] lariviere2008uclinux DL : 0: xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
Update : 2025-02-17 Size : 247kb Publisher : urga turg
[Windows Develop] 8BitRISC_CPU(VERILOG) DL : 0: 8位risc内核源代码，内有体统框图，较其他详细。适合初学者学习-8-bit risc kernel source code, there are decency diagram, compared with other details. Suitable for beginners to learn
Update : 2025-02-17 Size : 76kb Publisher : lsj
[VHDL-FPGA-Verilog] RISC_CPU DL : 0: Verilog写的简单处理器QuartusII下可编译 //指令操作码源寄存器目的寄存器操作 // NOP 0000 xxxxx xxxxxx 空操作 //ADD 0001 src dest dest<=src+dest //SUB 0010 src dest dest<=dest-src //AND 0011 src dest dest<=src&&dest //NOT 0100 src dest dest<=~src //RD 0101 xxxxx dest dest<= memory[Add_R] //WR 0110 src xxxxx memory[Add_R]<=src //BR 0111 xxxxx xxxxx PC<=memory[Add_R] //BRZ 1000 xxxxx xxxxx PC<=memory[Add_R] //HALT 1111 xxxxx xxxxx 挂起至RST-Verilog写的简单处理器QuartusII下可编译 //指令操作码源寄存器目的寄存器操作 // NOP 0000 xxxxx xxxxxx 空操作 //ADD 0001 src dest dest<=src+dest //SUB 0010 src dest dest<=dest-src //AND 0011 src dest dest<=src&&dest //NOT 0100 src dest dest<=~src //RD 0101 xxxxx dest dest<= memory[Add_R] //WR 0110 src xxxxx memory[Add_R]<=src //BR 0111 xxxxx xxxxx PC<=memory[Add_R] //BRZ 1000 xxxxx xxxxx PC<=memory[Add_R] //HALT 1111 xxxxx xxxxx 挂起至RST
Update : 2025-02-17 Size : 321kb Publisher : 魏文沫

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