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[VHDL-FPGA-Verilog] spi slave

Description: SPI 接口的VHDL和Verilog实现。slave模式
Platform: | Size: 4132 | Author: szsz06@126.com | Hits:

[VHDL-FPGA-Verilog] SPI_Code(Verilog)

Description: SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用-SPI bus under the Verilog hardware description language to achieve with the main mode and slave mode realization, through simulation, can be used as a separate module uses
Platform: | Size: 5120 | Author: 高兵 | Hits:

[SCM] mcu-cpld-spi

Description: mcu与cpld之间spi接口程序，mcu为master，cpld用verilog写成slave模块-mcu with spi interface program between the CPLD, mcu for the master, cpld written using Verilog slave module
Platform: | Size: 110592 | Author: 叶灿 | Hits:

[Other] spi.tar

Description: This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
Platform: | Size: 1024 | Author: johnl | Hits:

[Internet-Network] tongxinyuanli

Description: 数字通信原理 曹志刚版的SPI总线硬件描述语言Verilog下的实现，含主模式和从模式的实现，经过仿真验证，可作为一个单独的模块使用--Digital Communication Principles of CAO Zhi-gang version of the SPI bus, under the Verilog hardware description language implementation, including Master mode and slave mode of implementation, through the simulation can be used as a separate module--
Platform: | Size: 8550400 | Author: liusen | Hits:

[VHDL-FPGA-Verilog] VHD_Veri_spi

Description: 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequency. Support the host and slave mode, strongly recommended!
Platform: | Size: 13312 | Author: 中国 | Hits:

[VHDL-FPGA-Verilog] spi

Description: this the SPI slave module -this is the SPI slave module
Platform: | Size: 2782208 | Author: David | Hits:

[VHDL-FPGA-Verilog] SPI_Slave

Description: SPI Slave example (VERILOG HDL)
Platform: | Size: 1024 | Author: igor | Hits:

[VHDL-FPGA-Verilog] verilog-SPI-Controler

Description: 使用Verilog语言实现的SPI控制器，包括SPI主机和从机代码。-Using the Verilog language implementation of SPI controllers, including SPI master and slave codes.
Platform: | Size: 7168 | Author: 张秋光 | Hits:

[Com Port] verilog

Description: 介绍了一种SPI从机的接口verilog编码-verilog code for spi slave
Platform: | Size: 4096 | Author: 董广军 | Hits:

[VHDL-FPGA-Verilog] spislave_latest.tar

Description: SPI接口的verilog代码，本代码是从机代码。-SPI interface verilog code, the code is slave machine code.
Platform: | Size: 34816 | Author: 王远 | Hits:

[VHDL-FPGA-Verilog] SPI_fpga_w_r_sigle

Description: verilog fpga spi slave 收发测试 有简单的协议 modelsim仿真通过 -simple protocol modelsim verilog fpga spi slave transceiver test simulation by
Platform: | Size: 2650112 | Author: 飞天狐 | Hits:

[VHDL-FPGA-Verilog] spi

Description: spi slave verilog代码 spi slave verilog代码 spi slave verilog代码-spi slave verilog code spi slave verilog code spi slave verilog code
Platform: | Size: 1024 | Author: 何莉 | Hits:

[VHDL-FPGA-Verilog] SPI-Verilog-123

Description: spi slave code s pi slave code spi slave code -spi slave code spi slave code spi slave code spi slave code
Platform: | Size: 16384 | Author: 何莉 | Hits:

[VHDL-FPGA-Verilog] Nitro-Parts-lib-SPI-master

Description: Nitro-Parts-lib-SPI Verilog SPI master and slave
Platform: | Size: 5120 | Author: d.pershin | Hits:

[Embeded-SCM Develop] SPI

Description: SPI（Serial Peripheral Interface，串行外设接口）是Motorola公司提出的一种同步串行数据传输标准，是一种高速的，全双工，同步的通信总线，在很多器件中被广泛应用。 SPI相关缩写 SS: Slave Select，选中从设备，片选。 CKPOL (Clock Polarity) = CPOL = POL = Polarity = （时钟）极性 CKPHA (Clock Phase) = CPHA = PHA = Phase = （时钟）相位 SCK = SCLK = SCL = SPI的时钟（Serial Clock） Edge = 边沿，即时钟电平变化的时刻，即上升沿(rising edge)或者下降沿(falling edge)。 对于一个时钟周期内，有两个edge，分别称为： Leading edge = 前一个边沿 = 第一个边沿，对于开始电压是1，那么就是1变成0的时候，对于开始电压是0，那么就是0变成1的时候； Trailing edge = 后一个边沿 = 第二个边沿，对于开始电压是1，那么就是0变成1的时候（即在第一次1变成0之后，才可能有后面的0变成1），对于开始电压是0，那么就是1变成0的时候；(SPI (Serial Peripheral Interface, serial peripheral interface) is a synchronous serial data transmission standard put forward by Motorola company, is a high-speed, full duplex, synchronous communication bus, is widely used in many devices. SPI related abbreviations SS: Slave Select, selected from the device, chip select. CKPOL (Clock, Polarity) = CPOL = POL = Polarity = (clock) polarity CKPHA (Clock, Phase) = CPHA = PHA = Phase = (clock) phase SCK = SCLK = SCL = SPI clock (Serial, Clock) Edge = edge, instant clock, level change time, i.e. rising edge (rising, edge) or falling edge (falling, edge). For a clock cycle, there are two edge, respectively: Leading edge = front edge = first edge, for start voltage is 1, then 1 is 0, for start voltage is 0, then 0 is 1; Trailing = edge = second after an edge edge, the start voltage is 1, it is 0 to 1 of the time (that is, after the first 1 to 0, it may be behind the 0 to 1), the start voltage is 0, it is 1 to 0 times;)
Platform: | Size: 6144 | Author: helimpopo | Hits:

[Com Port] Master SPI的Verilog源代码(包括文档 测试程序)

Description: SPI接口的从机实现（利用verilog HDL语言）(Slave implementation of SPI interface (using Verilog HDL language))
Platform: | Size: 185344 | Author: 够歇斯底里吗 | Hits:

[VHDL-FPGA-Verilog] spi master slave

Description: SPI master slave (fpga/verilog)
Platform: | Size: 67584 | Author: taso999 | Hits:

[VHDL-FPGA-Verilog] spi_8r8w

Description: 同时实现多个SPI从设备的连续读写，读写字节数可变化(implement multiply spi slave read/write operation, and the operation's bytes can be changed)
Platform: | Size: 2048 | Author: zhou8848 | Hits:

[Embeded-SCM Develop] spi slave程序

Description: spi slave的verilog程序，有测试平台testbench程序，实现fpga作为salve的功能(spi slave verilog program)
Platform: | Size: 5120 | Author: CARL_2018 | Hits:
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