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[VHDL-FPGA-Verilog] Convolutional encoding and Viterbi decoding with k

Description: 卷积码编码和维特比解码 当K为7 时 供大家参考Convolutional encoding and Viterbi decoding with k 7 rate 1 2 -convolutional coding and Viterbi decoding when K 7:00 for reference convolutional encoding and Viterbi decoding with k 1 2 7 rate
Platform: | Size: 253952 | Author: 周小川 | Hits:

[VHDL-FPGA-Verilog] Viterbidecoder

Description: 维特比解码器低功耗设计verilog编码完整的程序可直接用-Viterbi decoder low power design Verilog coding complete procedures can be used directly
Platform: | Size: 386048 | Author: 杨艺 | Hits:

[VHDL-FPGA-Verilog] Viterbi_v

Description: Viterbi算法的Verilog源代码。-Viterbi Algorithm Verilog source code.
Platform: | Size: 11264 | Author: qjyong | Hits:

[Embeded-SCM Develop] viterbi_decoder_sources_code_verilog

Description: viterbi decoder , use verilog HDL language.-Viterbi decoder, use verilog HDL language.
Platform: | Size: 44032 | Author: 林四昆 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 介绍了viterbi译码器的编解码器的设计，包括decoder.v,encoder.v.control.v,ram.v等，压缩 包里面有pdf说明-Introduced a viterbi decoder codec design, including decoder.v, encoder.v.control.v, ram.v and so on, there are pdf compression package description
Platform: | Size: 62464 | Author: yaoyongshi | Hits:

[Communication-Mobile] Viterbi213

Description: 213viterbi译码的verilog语言实现-213viterbi decoding Verilog Language
Platform: | Size: 386048 | Author: 郭继经 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: (2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through
Platform: | Size: 10240 | Author: rxl | Hits:

[Other] viterbigen

Description: viterbi verilog 代码生成程序，产生多项式可自由指定-viterbi verilog code generation process, resulting in freedom of the specified polynomial
Platform: | Size: 53248 | Author: ryan zhang | Hits:

[VHDL-FPGA-Verilog] Viterbi_RAKE

Description: 这是一篇介绍用verilog语言实现viterbi译码和rake接收机的文章，实用性很强的，在这里也感谢这篇文章的作着-This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was
Platform: | Size: 8838144 | Author: 骆军 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 卷积码编码及其Viterbi译码的实现-Convolutional code encoder and Viterbi decoding to achieve
Platform: | Size: 256000 | Author: mediative | Hits:

[Communication-Mobile] viter2

Description: verilog实现卷积码的译码，viterbi算法-verilog to achieve the decoding convolutional codes, viterbi algorithm
Platform: | Size: 8192 | Author: 张洪 | Hits:

[Communication-Mobile] viterbi

Description: 一个vitrtbi算法的参考实现,verilog的-A reference implementation vitrtbi algorithm, verilog of
Platform: | Size: 62464 | Author: 张洪 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 这是一个用VERILOG HDL语言编写的viterbi译码程序-This is a language VERILOG HDL by the viterbi decoding process
Platform: | Size: 2048 | Author: chenxiaoming | Hits:

[Windows Mobile] viterbi

Description: viterbi encoder and decoder modeling verilog
Platform: | Size: 6144 | Author: glory | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: Viterbi verilog generator
Platform: | Size: 81920 | Author: zhanglh | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: verilog程序，实现了（2，1，4）卷积码编码，和基于回溯算法的维特比译码器-verilog program to achieve the (2,1,4) convolutional code encoding, and algorithm based on the back of the Viterbi decoder
Platform: | Size: 3072 | Author: xiongherui | Hits:

[VHDL-FPGA-Verilog] Viterbi_decoder

Description: Viterbi译码器的编解码器的设计 用Verilog实现-Viterbi decoder。Verilog
Platform: | Size: 64512 | Author: 李风飞 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: verilog code for viterbi encoder and decoder
Platform: | Size: 13312 | Author: kamran | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: This a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.-This is a code generator for some kinds of viterbi decoders. It can generate the synthesiable verilog HDL codes. These have been verified under simulation. The generator itself is released under GPL license but the Verilog HDL codes generated by it is without any restrictions except you MUST keep the license note in each Verilog HDL codes. I will be glad to head these Verilog HDL codes be used in some applications.
Platform: | Size: 654336 | Author: Nagendran | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 硬判决viterbi译码的硬件实现，通过verilog语言。采用回溯的方法。回溯深度为16.-Hard decision viterbi decoding in hardware, through the verilog language. A retrospective approach. Back depth is 16.
Platform: | Size: 92160 | Author: Fengxiaodong | Hits:
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