Description: 这是我电子线路测试的作业，在FPGA板上实现数字钟，（Max2环境）采用VHDL语言编写，非常适合初学者。具备24小时计时，校时，低高音整点报时，定时和多重功能选择的功能。-This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time, the school, the whole point of low Treble timekeeping, the timing and choice of multiple functional function. Platform: |
Size: 507269 |
Author:blacksun |
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Description: 这是我电子线路测试的作业，在FPGA板上实现数字钟，（Max2环境）采用VHDL语言编写，非常适合初学者。具备24小时计时，校时，低高音整点报时，定时和多重功能选择的功能。-This is my test of electronic circuits operating at the FPGA board digital clock (Max2 Environment) using VHDL language, very suitable for beginners. 24-hour time, the school, the whole point of low Treble timekeeping, the timing and choice of multiple functional function. Platform: |
Size: 506880 |
Author:blacksun |
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Description: 利用VHDL语言设计的数字钟,能进行正常的时、分、秒计时功能，分别由6个数码管显示24h、60min、60s-The use of VHDL language design digital clock, can be a normal hour, minute, second timing function, respectively, by 6 digital tube display 24h, 60min, 60s Platform: |
Size: 146432 |
Author:可爱 |
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Description: 描述了24小时计时的数字钟，同时具有分秒计时的功能-Described a 24-hour digital time clock, at the same time every minute timer function Platform: |
Size: 11264 |
Author:金珊珊 |
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Description: 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal. Platform: |
Size: 182272 |
Author:张保平 |
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Description: 24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program. Platform: |
Size: 382976 |
Author:张苏昕 |
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Description: 用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选，12小时制时有上下午指示；当计时到预定时间（此时间可手动设置）时，扬声器发出闹铃信号，闹铃时间为10秒，可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, optional 24-hour time system, 12-hour on the afternoon of instructions from time to time when the time to the scheduled time (This time can be manually set), the speaker sent alarm signals, alarm time was 10 seconds, the alarm can be terminated prematurely. Platform: |
Size: 382976 |
Author:旭东 |
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Description: 以前学EDA的时候做过的四个小程序，分别是24/12小时制数字钟、数字频率计、乐曲播放电路、多人智力竞赛抢答器-EDA previously done when the four small procedures are 24/12 hour digital clock, digital frequency meter, circuit music players and many more devices quiz Answer Platform: |
Size: 461824 |
Author:王宇 |
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Description: 本文档采用VHDL语言编写了一个数字时钟的程序，该数字时钟采用24小时制计时，可以实现整点报时，时间设置，闹钟等功能。最小分辨率为1秒。-VHDL language in this document using a digital clock to prepare the procedure, the digital clock 24-hour time system, you can bring the whole point of time, time settings, alarm clock functions. Minimum resolution of 1 second. Platform: |
Size: 680960 |
Author:cindy |
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Description: （1）用VHDL语言编写程序，在EDA实验板上实现
（2）能正常计时。显示模式分为两种，即24小时制和12小时制。其中12小时制须显示上，下午（用指示灯显示）。时，分，秒都要显示。
（3）. 手动校准电路。用一个功能选择按钮选择较时，分功能，用另一个按钮调校对应的时和分的数值。
用VHDL语言编写程序，在EDA实验板上实现
（4） 整点报时。
（5）. 闹钟功能。
（6）．秒表功能。-(1) using VHDL language program, in the EDA experiments on-board implementation (2) to resume normal time. Display mode is divided into two kinds, namely, a 24-hour system and 12-hour clock. Including 12-hour clock to be displayed on the afternoon (with light display). Hours, minutes and seconds to be displayed. (3). Manual calibration circuit. With a select button to choose a more functional hours, minutes functions, with another button to adjust the corresponding time and sub-values. Using VHDL language programs, in the EDA experiments on-board implementation (4) The whole point timekeeping. (5). Alarm. (6). Stopwatch function. Platform: |
Size: 4096 |
Author:malon |
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Description: 用硬件描述语言实现数字钟的设计，实现正常计时，报整点时数，电台整点报时，12小时制与24小时制转换等功能。其中有代码和仿真结果-Using hardware description languages digital clock design, implement the normal timing, the whole point, the number of newspaper, radio and the whole point timekeeping, 12-hour and 24-hour conversion functions. Including code and simulation results Platform: |
Size: 207872 |
Author:张军 |
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Description: 基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。-FPGA-based design of digital electronic clock, the system program by the total frequency module, " the minutes and seconds" counter module, data selection module, timer module, dynamic scanning display and decoding module. Get a will " ," and " division" and " seconds" display on the human visual organ of the timing device. It' s time for the 24-hour period, indicating full scale as 23:59:59, and another school, the school hours and the whole hour, and through digital tube display driver circuit timing results. Platform: |
Size: 63488 |
Author:sunnan |
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Description: 数字钟的VHDL语言实现基本功能，包括
1、24小时计数显示；
2、具有校时功能（时，分） ；
附加要求：
1、实现闹钟功能（定时，闹响）；
-Digital clock in the VHDL language for basic functions, including 1,24-hour count display 2, when a school function (hour, minute) additional requirements: 1, to achieve the alarm function (time, alarm sound) Platform: |
Size: 1024 |
Author:xiezunzhong |
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Description: 用VHDL语言编写的12/24小时时钟，利用EDA系统软件QuartusII环境下基于FPGA/CPLD的数字系统设计方法-VHDL language with the 12/24 hour clock, the use of EDA software QuartusII environment based on FPGA/CPLD design of digital system Platform: |
Size: 2106368 |
Author:Cherry |
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Description:
要求设计一个带闹钟功能的24小时计时器
它包括以下几个组成部分：
① 显示屏：4个七段数码管显示当前时间(时：分)或设置的闹钟时间；一个发光二极管以1HZ的频率跳动，用于显示秒；
② 按键key1，用于设置调时还是调分；
③ 按键key2，用于输入新的时间或新的闹钟时间，每按下一次，时或分加1；
④ TIME(时间)键，用于确定新的时间设置；
⑤ ALARM(闹钟)键，用于确定新的闹钟时间设置，或显示已设置的闹钟时间；
⑥ 扬声器，在当前时钟时间与闹钟时间相同时，发出蜂鸣声。
-To design a 24-hour alarm clock with a timer which includes the following components: ① Display: 4 segment digital tube displays the current time (hours: minutes) or set the alarm time a light-emitting diode to the frequency of 1HZ beating, is used to display seconds ② keys key1, when used to set the tone or the tone pm ③ key key2, used to enter the new time or a new alarm time, every time you press, or points plus 1 ④ TIME ( time) key, used to determine the new time settings ⑤ ALARM (alarm) button, used to determine a new set alarm time, or set the alarm time is displayed ⑥ Speaker, in the current time and alarm clock the same time, issue beep. Platform: |
Size: 259072 |
Author:洪巨成 |
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Description: 使用vhdl语言设计电子钟。具有时、分、秒计数功能，且以24小时循环计时。计时结果要用6个数码管分别显示时、分、秒的十位和个位。具有清零功能。
-Use vhdl languages designed electronic clock. Has hours, minutes, seconds count and a 24-hour cycle timing. The timing results use six digital tube display hours, minutes, seconds, ten and a bit. Has a clear function. Platform: |
Size: 322560 |
Author:陈小龙 |
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Description: 用VHDL语言实现12/24小时制数时钟，可显示时、分、秒；能够进行整点报时，具有12/24小时切换功能-Number of 12/24 hour clock clock using VHDL, can display hours, minutes, seconds able to carry out the whole point of time, with 12/24 hour switch Platform: |
Size: 2287616 |
Author:王婷 |
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Description: （1）24小时计时显示（时分秒）；
（2）具有时间设置功能（时，分） ；
（3）具有整点提示功能；
（4）实现闹钟功能（定时，闹响）；((1) 24 hour time display (time, minute, second);
(2) have time setting function (time and minute);
(3) it has the function of whole point.
(4) realize the alarm clock function (timing, noise);) Platform: |
Size: 4346880 |
Author:Goddd |
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Search - vhdl 24 hour clock