Description: MIPS处理器VHDL代码，实现加法，减法乘除等运算，可综合，-MIPS processor VHDL code, realize adder, subtraction multiplication and division and other operations can be integrated, Platform: |
Size: 6144 |
Author:陈丰 |
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Description: 此程序采用VHDL语言，完成在16位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的16位二进制加法器-This procedure using VHDL language, completed in 16-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 16 binary adder Platform: |
Size: 1024 |
Author:韩善华 |
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Description: 此程序采用VHDL语言，完成在32位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的32位二进制加法器-This procedure using VHDL language, completed in 32-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 32 binary adder Platform: |
Size: 1024 |
Author:韩善华 |
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Description: 一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加-A 32-bit floating-point adder can be both within the IEEE 754 format to add value Platform: |
Size: 10240 |
Author:TTJ |
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Description: 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved! Platform: |
Size: 278528 |
Author:王强 |
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Description: 8位cla，采用for结构，可以扩张成32位或者16位-8 cla, used for the structure, you can expand into a 32-bit or 16-bit Platform: |
Size: 36864 |
Author:sigma |
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Description: 本设计是做了一个32位超前进位加法器，能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate Platform: |
Size: 38912 |
Author:zhaozimou |
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Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder. Platform: |
Size: 154624 |
Author:凌音 |
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Description: 32位加法器，基于vhdl语言，主要用于测试算法-32-bit adder, based on the vhdl language, mainly used for testing algorithms Platform: |
Size: 2215936 |
Author:zhang |
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Description: 基于VHDL语言，编写一个32位全加器文件，可直接编译-Based on VHDL language, write a 32-bit full adder files can be directly compile Platform: |
Size: 497664 |
Author:zhang |
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Description: 此程序源码使用VHDL语言，完成在32位十六进制加法器的基础上将输出出进行BCD码转换，实现输出是BCD码的32位二进制加法 可直接使用。
-This program source code using VHDL language, completed on the basis of 32-bit hexadecimal adder output BCD code conversion, the output is a 32-bit binary adder BCD code can be used directly. Platform: |
Size: 1024 |
Author:分配 |
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Description: This a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA).-This is a code that describe 32 bit carry look ahead adder in VHDL(32 bit CLA). Platform: |
Size: 1024 |
Author:hskim |
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Description: The Vedic mathematics is quite different from
conventional method of multiplication like adder and shifter.
This mathematics is mainly based on sixteen principles. The
multiplier (referred henceforth as Vedic multiplier)
architecture based on the URDHVA TIRYAKBHYAM
(Vertically and cross wise) sutra is presented. The existing
method is 16*16 bit multiplication in relatively less speed. The
proposed method is 32*32 bit multiplication in terms of
relatively high speed, low power, less area and less delay. This
will help in designing multiplier in VHDL, as its give effective
utilization of structural method of modelling. This also gives
chances for modular design where smaller block can be used to
design the bigger one.-The Vedic mathematics is quite different from
conventional method of multiplication like adder and shifter.
This mathematics is mainly based on sixteen principles. The
multiplier (referred henceforth as Vedic multiplier)
architecture based on the URDHVA TIRYAKBHYAM
(Vertically and cross wise) sutra is presented. The existing
method is 16*16 bit multiplication in relatively less speed. The
proposed method is 32*32 bit multiplication in terms of
relatively high speed, low power, less area and less delay. This
will help in designing multiplier in VHDL, as its give effective
utilization of structural method of modelling. This also gives
chances for modular design where smaller block can be used to
design the bigger one. Platform: |
Size: 172032 |
Author:farbosein |
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Search - vhdl 32 bit adder