Search - vhdl ADD

[Other resource] ADD

Description: 在MAX+PLUS II环境下用VHDL编写的加法器
Platform: | Size: 35062 | Author: 林超勇 | Hits:

[VHDL-FPGA-Verilog] 8bit Cpu designing

Description: CPU具有的功能：能完成一些简单的指令 MOV AX,ADDRESS4 --将address4中的内容赋给AX寄存器（在8086/8088汇编语言中称这种寻址方式为直接寻址方式） ADD AX,ADDRESS4 -- 将address4中的内容加到AX寄存器中 SUB AX,ADDRESS4 -- 用address4中的内容减去AX寄存器中的内容 OUT -- 输出AX寄存器中的内容 HLT -- CPU停止运行
Platform: | Size: 103424 | Author: kinglord2006@sina.com | Hits:

[VHDL-FPGA-Verilog] add_multi

Description: 移位相加硬件乘法器,基于FPGA的VHDL语言编写的,含有全部文件-displacement add hardware multiplier, based on FPGA VHDL prepared, containing all the documents
Platform: | Size: 3072 | Author: 相耀 | Hits:

[Software Engineering] LPM_sub_add

Description: VHDL中IP核之参数化加减法器中文使用介绍-VHDL IP parameters of the nuclear modified instruments used on the use of Chinese
Platform: | Size: 146432 | Author: 孙彬 | Hits:

[VHDL-FPGA-Verilog] magnitude

Description: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Platform: | Size: 12288 | Author: 郝晋 | Hits:

[VHDL-FPGA-Verilog] VGAcontrol

Description: alter控制VGA输出VHDL源代码使用方法： 1.拷贝到硬盘，用Quartus中新建工程，添加文件即可。-alter control VGA output VHDL source code to use: 1. copy to your hard disk, using Quartus in new construction, you can add files.
Platform: | Size: 38912 | Author: 张丽滨 | Hits:

[Multimedia program] video_compression_systems.tar

Description: 视频、图像压缩代码，内附使用说明，建立相应工程后，将Verilog代码ADD之后就可以编译调试，对于学习图像压缩或熟悉FPGA调试环境的人员会有一定的帮助-Video, image compression code, containing instructions to establish the corresponding work will Verilog code can be compiled after ADD debugging, for learning image compression, or are familiar with FPGA debug environment will help staff
Platform: | Size: 186368 | Author: 王弋妹 | Hits:

[VHDL-FPGA-Verilog] vga_system

Description: FPGA读写SDRAM的实例，可以当作IPcore来添加，非常有价值的的程序。-FPGA examples SDRAM read and write, can be used as IPCore to add, a very valuable process.
Platform: | Size: 21392384 | Author: 陈泸华 | Hits:

[VHDL-FPGA-Verilog] ADD

Description: 在MAX+PLUS II环境下用VHDL编写的加法器-In MAX+ PLUS II environment prepared using VHDL Adder
Platform: | Size: 34816 | Author: 林超勇 | Hits:

[File Format] modelcomputer

Description: 基于模型机的设计，进行简单的CPU设计并实现基本的指令，如加、减、转移等。-Model-based design, a simple CPU design and realization of the basic commands, such as add, subtract, transfer.
Platform: | Size: 287744 | Author: 刘金玲 | Hits:

[VHDL-FPGA-Verilog] LowpassfilterVHDLcord

Description: 低通滤波器的VHDL代码，需要的可以下来看看，本人QQ147440013，有志同道合的人可以加我哦-Low-pass filter of the VHDL code, need to take a look at the can down, I QQ147440013, have like-minded people can add me, oh
Platform: | Size: 4096 | Author: 黄建 | Hits:

[VHDL-FPGA-Verilog] oc_i2c_master

Description: 用VHDL制作的I2C控制器，是一个component,之间添加就可以使用。-VHDL produced using I2C controller, is a component, you can use to add between.
Platform: | Size: 386048 | Author: 辛小怡 | Hits:

[ARM-PowerPC-ColdFire-MIPS] MIPStest00

Description: 簡易MIPS CPU程式碼此CPU包含 shift add sub and or stl beq lw sw 等功能-Simple MIPS CPU code for this CPU contains shift add sub and or stl beq lw sw functions
Platform: | Size: 7168 | Author: chen | Hits:

[VHDL-FPGA-Verilog] add(FLP)

Description: 一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加-A 32-bit floating-point adder can be both within the IEEE 754 format to add value
Platform: | Size: 10240 | Author: TTJ | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 支持十条指令的微处理器包括add sub mov mvi jmp jz in out sti lda微指令支持8个寄存器 16位数据总线地址总线 -Supports 10 microprocessor instructions, including add sub mov mvi jmp jz in out sti lda microinstruction registers support 8 data bus 16-bit address bus
Platform: | Size: 1074176 | Author: 张梦 | Hits:

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