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Description: An encoder/decoder for binary BCH codes
Error correction using the BERLEKAMP-MASSEY ALGORITHM.Any (valid) code length can be input-An encoder/decoder for binary BCH codes Er Ryan correction using the BERLEKAMP- MASSEY ALG ORITHM.Any (valid) code length can be input
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Size: 5120 |
Author: 里海 |
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Description: 给出BCH编码和译码的原理
以及解决方案，特别是仿真的一种解决方案，值得参考。-BCH coding and decoding given the principle, as well as solutions, in particular the simulation of a solution, it is also useful.
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Size: 1024 |
Author: liu |
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Description: bch码编译码中多个代数余子式的计算
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Size: 1024 |
Author: luvicee |
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Description: BCH编码器并行8路实现，速率达到300M以上-BCH encoder realize 8-channel parallel, the rate reached more than 300M
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Size: 2048 |
Author: 张凯斌 |
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Description: 这是我做的一个BCH译码模块硬件语言模块，这么好的东西上传上来还不让下载-This is what I do a BCH decoding hardware module language module, so good things do not let up upload download
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Size: 7168 |
Author: WuLiangMing |
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Description: BCH代码，采用VHDL实现，能够实现纠错，带有波形。-BCH code, the use of VHDL implementation, be able to achieve error correction with waveform.
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Size: 206848 |
Author: daisy |
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Description: BCH编码 实现BCH信道编码功能 实现BCH信道编码功能-BCH code BCH code BCH code BCH code BCH code BCH code BCH code
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Size: 933888 |
Author: p2pover |
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Description: BCH码的编码和解码全部过程的源代码，可以自行改变参数-BCH codes of all the process of encoding and decoding of the source code, can change the parameters
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Size: 8192 |
Author: 郎咸平 |
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Description: 这是用verilog编写的RS（204，188）代码，适用于数字电视的BCH编码过程。-This is the verilog prepared using RS (204,188) code, the application of digital television in the course of the BCH code.
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Size: 2048 |
Author: 蕊宫獍雪 |
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Description: bch 编码和译码，用硬件语言vhdl实现-bch edcode and decoder
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Size: 175104 |
Author: 唐娇 |
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Description: example of codec BCH(15,7)
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Size: 7168 |
Author: hidon |
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Description: example of codec BCH(15,11)
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Size: 12288 |
Author: hidon |
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Description: example of BCH and RS codecs
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Size: 303104 |
Author: hidon |
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Description: The attached file consists of implimentation of BCH codes in VHDL programming using XILINX software.
This code will reduce the no. of gates requirement.
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Size: 13312 |
Author: babi |
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Description: The attached file consists of double error correcting bch code.this code will save number gates required for implimentation
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Size: 411648 |
Author: babi |
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Description: Viterbi based trellis decoder for (7,4) - binary BCH code-Viterbi based trellis decoder for (7,4)- binary BCH code
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Size: 1024 |
Author: shahifaqeer |
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Description: Experimental report VHDL VHDL verilog rs flip-flop experiment experimental report VHDL VHDL verilog rs flip-flop experiment
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Size: 15360 |
Author: santhu |
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Description: Syntetizable source code of VHDL BCH(1023,1013) encoder. This scheme used by DTMB standart and produce ten redundancy bit on 125 cycles because bus width of 8 bits.
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Size: 8192 |
Author: Juan |
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Description: bch encode and decode wit error correction for bch(255,233)
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Size: 1741824 |
Author: sandeep |
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Description: In this project, we are implementing the error detection and correction using BCH code (Bose Chaudhuri Hocquenghem). Using VHDL and targeted on FPGA for synthesis of the code. The encoder and decoder combine called as a codec.
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Size: 6164480 |
Author: venkata vijay |
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