Search - vhdl code for uart

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[VHDL-FPGA-Verilog] conv_code DL : 0: 用VHDL实现卷积码编码，该码为（2.1.3）型卷积码。-using VHDL Convolutional coding, the code (2.1.3)- Convolutional Codes.
Update : 2025-02-17 Size : 1kb Publisher : 武汉
[Com Port] uart_VHDL DL : 0: uart的vhdl实现代码分模块设计和状态机设计不错的，用它没错-UART achieve the VHDL code modular design and state machine design good, the right to use it
Update : 2025-02-17 Size : 10kb Publisher : 王平
[VHDL-FPGA-Verilog] u-uart DL : 0: 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
Update : 2025-02-17 Size : 5kb Publisher : 李文文
[VHDL-FPGA-Verilog] usingVHDLtoimplementUART DL : 0: Update : 2025-02-17 Size : 310kb Publisher : 邓旭
[VHDL-FPGA-Verilog] uart DL : 0: vhdl书写uart代码,经验证功能非常的全.-UART code written in VHDL, experience card features a very wide.
Update : 2025-02-17 Size : 396kb Publisher : zjc
[VHDL-FPGA-Verilog] UART232 DL : 0: 本代码是用VHDL语言全面、系统地描述UART通信协议标准，通过对UART进行数据通信的实际运用，能够较全面地理解和掌握VHDL和UART协议。-The VHDL language code is a comprehensive, systematic description of UART communication protocol standards, through the UART to the practical application of data communications, to more fully understand and grasp the VHDL and the UART protocol.
Update : 2025-02-17 Size : 22kb Publisher : fengxinya
[VHDL-FPGA-Verilog] 8051-vhdl-code DL : 0: Update : 2025-02-17 Size : 96kb Publisher : 周华茂
[Com Port] uart DL : 0: 开源的串口通信程序，用vhdl 编写的，已通过测试，在DE2的开发板上能够运行。-Open source serial communication procedures, prepared by using VHDL, has been tested in the DE2 development board to run.
Update : 2025-02-17 Size : 2kb Publisher : caijl88
[VHDL-FPGA-Verilog] uart DL : 0: vhdl语言编写的实现uart协议的程序,用于rs232电气接口程序开发.支持比特率从2400-115200.-VHDL languages realize UART protocol procedures, electrical RS232 interface for program development. to support the bit rate from 2400-115200.
Update : 2025-02-17 Size : 5kb Publisher : 陈想
[VHDL-FPGA-Verilog] uart DL : 0: VHDL编写的异步通信串行口设计用Quartus工具编译-VHDL prepared the design of serial asynchronous communication tool used Quartus compiler
Update : 2025-02-17 Size : 208kb Publisher : 朱兆斌
[SCM] uart DL : 0: 单片机串口通信原理，对于初学者来说是很好的资料。-Single-chip serial communication principle is very good for beginners information.
Update : 2025-02-17 Size : 55kb Publisher : liujuan
[VHDL-FPGA-Verilog] uart(Verilog) DL : 0: uart异步串口通信协议的源代码，用vhdl语言编写，并且有完整得测试文件-UART asynchronous serial communication protocol source code, using VHDL language, and may have a complete test file
Update : 2025-02-17 Size : 10kb Publisher : 阿军
[VHDL-FPGA-Verilog] UART DL : 0: 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
Update : 2025-02-17 Size : 331kb Publisher : 韩思贤
[Com Port] UART DL : 0: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Update : 2025-02-17 Size : 9kb Publisher : 李佳
[VHDL-FPGA-Verilog] uart DL : 0: Verilog编写的UART程序源代码。测试成功。支持字符串发送-UART prepared Verilog source code. Successful test. Support string sent
Update : 2025-02-17 Size : 1.48mb Publisher : 卢山
[VHDL-FPGA-Verilog] URAT_VHDL_CODE DL : 1: altera公司的fpga源代码，用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.
Update : 2025-02-17 Size : 32kb Publisher : 张东
[VHDL-FPGA-Verilog] uart DL : 0: uart - universal asynchronous receicer and transmitter source code using VHDL
Update : 2025-02-17 Size : 1.84mb Publisher : nagarjuna reddy
[Other] uart DL : 0: UART串口的VHDL源程序，希望对大家有用-UART serial port of the VHDL source code, we want to be useful
Update : 2025-02-17 Size : 17kb Publisher : 贾明
[VHDL-FPGA-Verilog] gh_uart_16550_072108 DL : 0: UART（通用串行收发器）的VHDL源代码，适合硬件工程师在FPGA内部实现多个UART-UART (universal serial transceivers), VHDL source code for hardware engineers in the FPGA to achieve multiple internal UART
Update : 2025-02-17 Size : 16kb Publisher : 彭涛
[VHDL-FPGA-Verilog] uart DL : 0: VHDL CODE FOR UART IN DEEP MODIFIED
Update : 2025-02-17 Size : 284kb Publisher : ranveer

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