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[Other resource] CPLDxiaoche

Description: 智能机器小车主要完成寻迹功能，由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分，采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要利用ULN2803作为驱动芯片。 -intelligent machines trolley track of the major functions by mechanical structure and control modules of two components. Mechanical structure is a chassis, after supporting wheels, the control panel stent, sensors stent, driving wheel around, Stepper motors, and other components. Some of the main control unit from the mainly contains sensors and conditioning circuits, and stepper motor drive circuit, the controller of three parts. The design for the core controller, Altera MAX7000S the EPM7064LC84-15 for the control chip. CPLD chip design mainly in MAX II plus 10.0 environment using VHDL programming. Stepper motor driver circuit using mainly driven ULN2803 chip.
Platform: | Size: 1369 | Author: lili | Hits:

[VHDL-FPGA-Verilog] CPLDxiaoche

Description: 智能机器小车主要完成寻迹功能，由机械结构和控制单元两个部分组成。机械结构是一个由底盘、前后辅助轮、控制板支架、传感器支架、左右驱动轮、步进电机等组成。控制单元部分主要由主要包含传感器及其调理电路、步进电机及驱动电路、控制器三个部分。本设计的核心为控制器部分，采用Altera MAX7000S系列的EPM7064LC84-15作主控芯片。CPLD芯片的设计主要在MAX+plusⅡ10.0环境下利用VHDL语言编程实现。驱动步进电机电路主要利用ULN2803作为驱动芯片。 -intelligent machines trolley track of the major functions by mechanical structure and control modules of two components. Mechanical structure is a chassis, after supporting wheels, the control panel stent, sensors stent, driving wheel around, Stepper motors, and other components. Some of the main control unit from the mainly contains sensors and conditioning circuits, and stepper motor drive circuit, the controller of three parts. The design for the core controller, Altera MAX7000S the EPM7064LC84-15 for the control chip. CPLD chip design mainly in MAX II plus 10.0 environment using VHDL programming. Stepper motor driver circuit using mainly driven ULN2803 chip.
Platform: | Size: 1024 | Author: lili | Hits:

[VHDL-FPGA-Verilog] controlunit

Description: CPU设计中的controlunit源码，其中附带了时序仿真。通过Sequencing Logic 产生 control_signals,具体的信号可在controlsignal.mif文件中直接修改。 -CPU design controlunit source, which comes with timing simulation. Sequencing Logic generated through control_signals, specific signals can directly modify the controlsignal.mif document.
Platform: | Size: 328704 | Author: ck | Hits:

[VHDL-FPGA-Verilog] uart

Description: M_UART 介绍了通用异步收发器（UART）的原理，并以可编程逻辑器件FPGA为核心控制部件，基于超高速硬件描述语言VHDL在Xilinx公司的SpartanⅡ系列的2sc200PQ208-5芯片上编程完成UART的设计。经测试，该设计完全达到了设计要求。-M_UART introduce a Universal Asynchronous Receiver Transmitter (UART) Principle and FPGA programmable logic device as the core control unit, based on the ultra-high-speed hardware description language VHDL in Xilinx
Platform: | Size: 18432 | Author: lc | Hits:

[VHDL-FPGA-Verilog] freq

Description: 智能频率计 1. 频率测量范围为1Hz~1MHz 2. 当频率在1KHz以下时采用测周方法 其它情　　 　　况采用测频方法.二者之间自动转换 3. 测量结果显示在数码管上,单位可以是Hz（Ｈ）、　 　　KHz（ＡＨ）或MHz（ＢＨ）。 ４. 测量过程不显示数据，待测量结果结束后，直接显示结果。 -Intelligent frequency meter 1. Frequency measurement range of 1Hz ~ 1MHz 2. When the frequency of 1KHz weeks following measurement methods used in other circumstances the use of frequency measurement methods. Automatically switch between the two 3. Measurement results have shown that in the digital control, the unit can be Hz (H), KHz (AH) or MHz (BH). 4. Measurement process does not display data until after the end of the measurement results, the direct result will be displayed.
Platform: | Size: 238592 | Author: 谭超 | Hits:

[Windows Develop] CPU

Description: RC4 Encrpytion 1.Encrpyt strings 2.Create pairs of keys for encoding and decoding automatically 3.Present the crptograph 4.Decode the crptograph to get the plaintext -This CPU has basic instruction set, and we utilize its instruction set to generate a program to verify its performance. Four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set.
Platform: | Size: 34816 | Author: Jane | Hits:

[SCM] shukongzhiliudianyuan

Description: 介绍了一种闭环智能数控直流电流源的设计原理和实施方案，该方案采用自行设计制作的高精度电压源，利用单片机、PWM和运算放大器构成A/DD/A转换器来控制场效应管导通状态的原理，达到了输出恒流的目的。整个系统采用89C58单片机作为主控部件，将预置电流值数据送入D/A转换器，经硬件电路变换为恒定的直流输出，同时使用采样电阻将实际输出电流转换成电压送入A/D转换器，并将其反馈到单片机中构成闭环系统，进而实现预设值和实际值的比较，再通过调整D /A转换器输出的电压来改变场效应管的导通状态，减小了实际值与预设值之间的误差，实现了电流可预置、可步进调整、输出的电流信号可直接数字显示的功能。采用硬件闭环、软件闭环、软件实时积分、实时滤波的方法，锁定输出电流，从而实现了高精度恒流源的目的。此次所设计的电流源具有精度高、结构简单、工作稳定、操作方便、成本低廉、带负载能力强等优点-The scheme adapts high precision voltage source designed by ourselves Micro Control Unit (MCU) D/A converter and amplifier to control the transmitting state of field effect transistor which attains constant current. The system adapts MCU 89c52 as main control part the output current is transformed into the voltage by sample resistant and the voltage is sent to D/A converter and then sent to the MCU compared with the setting current. If there exist errors we should adapt D/A converter output and change the transmitting state of field effect transistor. The actual value is directed to the setting value. The direct current reaches the constant value. The closed loop control and PID arithmetic is used to realize high precision and wide range in the software design part. The intelligent current source realizes that the output current can be preset adjusted step by step and displayed in digit directly. Above functions are operated by keyboard within the current source. The stability of this
Platform: | Size: 2048 | Author: zhendongzhao | Hits:

[Windows Develop] CONTROL_UNIT

Description: control unit for multicycle cpu
Platform: | Size: 1024 | Author: a | Hits:

[VHDL-FPGA-Verilog] 16bitalu

Description: 16 bit alu using the vhdl it has 16 function perform by control unit with 4 control signal
Platform: | Size: 1002496 | Author: jai | Hits:

[Software Engineering] fpgada0832

Description: 该波形发生器以单片机(MCS8031)为中心控制单元，由键盘输入模块、数码管显示模块、D/A波形发生模块dac0832、幅值调整模块组成。采用DDFS技术，先将要求的波形数据存储于EEPROM中，这样可以保证掉电以后波形数据不丢失。-The waveform generator to single-chip microcomputer (MCS8031) as the central control unit, by the keyboard input module, digital tube display module, D/A waveform occurred in module, the amplitude adjustment module. DDFS technology used, first the requirements of waveform data stored in EEPROM, so that after power-down waveform to ensure that data is not lost.
Platform: | Size: 172032 | Author: litong | Hits:

[Technology Management] controlunit

Description: its a simple control unit source code for a basic microprocessor.
Platform: | Size: 1024 | Author: rajeev | Hits:

[Other Embeded program] zdshj

Description: 自动售货机控制系统设计 要求： 设计制作一个自动售货机控制系统。 该系统能完成货物信息存储，进程控制，硬币处理，余额计算，显示等功能。 该系统可以管理四种货物，每种的数量和单价在初始化时输入，在存储器中存储。用户可以用硬币进行购物，按键进行选择。 系统根据用户输入的货币，判断钱币是否够，钱币足够则根据顾客的要求自动售货，钱币不够则给出提示并退出。 系统自动的计算出应找钱币余额、库存数量并显示。 -Vending machine control system design requirements: Design a vending machine control system. The system can complete cargo information storage, process control, coin handling, balance calculation, display and other functions. The system can manage four kinds of goods, the quantity and unit price of each in the initialization input, stored in memory. Users can use coins shopping button to choose. The monetary system based on user input to determine whether enough money, coins, according to customer requirements is sufficient Vending, coins were not given prompt and exit. The system automatically calculate the balance should be looking for coins, inventory number and displayed.
Platform: | Size: 67584 | Author: dws | Hits:

[SCM] buy_candy

Description: Let us design a control unit for a simple coin-operated candy machine. Candy costs 20 bath ,and the machine accept 5 bath and 10 bath. Change should be return if less than 5 bath is deposited. No more than 25 bath can be deposited on a single purchase therefore ,the maximum change is 5 bath.-Let us design a control unit for a simple coin-operated candy machine. Candy costs 20 bath ,and the machine accept 5 bath and 10 bath. Change should be return if less than 5 bath is deposited. No more than 25 bath can be deposited on a single purchase therefore ,the maximum change is 5 bath.
Platform: | Size: 1024 | Author: adearong | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 设计以及基本的CPU，至少包括四个基本单元，控制单元，内部寄存器，ALU和指令集-The purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions. At least four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instruction set, which are the main aspects of our project design and will be studied.
Platform: | Size: 2196480 | Author: mollyma | Hits:

[MiddleWare] multiplier

Description: a multiplier in vhdl, contains an alu and a control unit
Platform: | Size: 2048 | Author: george | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 介绍Verilog HDL, 内容包括：Verilog应用，Verilog语言的构成元素，结构级描述及仿真 ，行为级描述及仿真，延时的特点及说明 介绍Verilog testbench，激励和控制和描述 结果的产生及验证，任务task及函数function 用户定义的基本单元(primitive)，可综合的Verilog描述风格等-Introduction Verilog HDL, including: Verilog applications, Verilog language of the elements, structure, level description and simulation, behavioral-level description and simulation, delay characteristics and note describes Verilog testbench, described the results of incentive and control and the generation and verification, the task task and function of the basic unit of user-defined function (primitive), can be integrated Verilog description of style
Platform: | Size: 1521664 | Author: shirley | Hits:

[VHDL-FPGA-Verilog] can_latest[1].tar

Description: CAN，全称“Controller Area Network”，即控制器局域网，是国际上应用最广泛的现场总线之一。最初，CAN被设计作为汽车环境中的微控制器通讯，在车载各电子控制装置ECU之间交换信息，形成汽车电子控制网络。比如：发动机管理系统、变速箱控制器、仪表装备、电子主干系统中，均嵌入CAN控制装置。 -CAN, full name of the " Controller Area Network" , the Controller Area Network, is internationally the most widely used field bus. Initially, CAN is designed as a vehicle environment, the micro-controller communications, in-vehicle electronic control unit ECU of the exchange of information between the formation of automotive electronic control network. For example: engine management systems, transmission controllers, instrumentation and equipment, electronic backbone of the system are embedded CAN control.
Platform: | Size: 1149952 | Author: zhaohaiting | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 本设计中应用硬件描述语言Verilog HDL描述相位累加器，相位调制器，正弦波、方波、三角波、心电波形四个独立的波形存储器，并描述频率控制、相位控字、幅度控制单元及波形切换等相关的功能单元。-Application of the design described in Verilog HDL hardware description language phase accumulator, phase modulator, sine, square, triangle wave, the four independent ECG waveform memory, and describe the frequency control, phase control word, control unit and the waveform amplitude switching and other related functional units.
Platform: | Size: 4096 | Author: kelly | Hits:

[VHDL-FPGA-Verilog] DiSyLab2

Description: A vhdl design of a simple control unit
Platform: | Size: 602112 | Author: vasoggr | Hits:

[VHDL-FPGA-Verilog] 6soft_247MHz_channel

Description: lte上行信道解交织解复用: RTL: ack_addr_gen.vhd ack地址产生 data_addr_gen.vhd 数据地址产生 de_interl_mux_con_ctrl.vhd 控制单元 de_interl_mux_con_top.vhd 顶层 de_interl_mux_con_tt.vhd 测试平台 de_mux_ram.vhd ram deinterl_pack.vhd 变量定义 delay.vhd 延迟 delayb.vhd 延迟 input_buffer.vhd 输入控制 ri_addr_gen.vhd ri信息提取 ul_common_pack.vhd 变量定义 write_ram.vhd 解交织 deintlv_data.txt 数据源 deintlv_data_ack.txt ack信息源 deintlv_data_cqi.txt cqi信息源 deintlv_data_ri.txt ri信息源 sim_lib.tcl altera库编译 ue.tcl modelsim 脚本-upstream channel deinterleaving lte demultiplexing: RTL: ack_addr_gen.vhd ack address generation data_addr_gen.vhd data address generation control unit de_interl_mux_con_top.vhd de_interl_mux_con_ctrl.vhd top de_interl_mux_con_tt.vhd test platform de_mux_ram.vhd ram deinterl_pack.vhd delay variable definition delay.vhd delayb.vhd delay input_buffer.vhd input control information extraction ul_common_pack.vhd ri_addr_gen.vhd ri definition of a variable data source write_ram.vhd deinterleaving deintlv_data.txt deintlv_data_cqi.txt cqi deintlv_data_ack.txt ack information source information sources sources of information deintlv_data_ri.txt ri sim_lib. tcl altera library compile script ue.tcl modelsim
Platform: | Size: 200704 | Author: renliang | Hits:
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