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[Other resource] VHDLDPLL

Description: 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.
Platform: | Size: 168107 | Author: 李湘鲁 | Hits:

[Other resource] 200761311574149479

Description: 介绍了如何使用数字锁相环,如何用VHDL实现数字锁相环-on how to use the DPLL, how to use VHDL DPLL
Platform: | Size: 63234 | Author: zhaojia | Hits:

[VHDL-FPGA-Verilog] pll

Description: 用VHDL写的数字锁相环程序 pll.vhd为源文件 pllTB.vhd为testbench-pll.vhd : PLL written in VHDL hardware language. pllTB.vhd is a test program for pll.vhd.
Platform: | Size: 111616 | Author: 孙犁 | Hits:

Description: 简单的可配置dpll的VHDL代码。用于时钟恢复后的相位抖动的滤波有很好的效果，而且可以参数化配置pll的级数。-simple configurable dpll VHDL code. Clock Recovery for the jitter filtering is a very good result, but can pll configuration parameters of the series.
Platform: | Size: 2048 | Author: 陈德炜 | Hits:

[Software Engineering] 010919.pdf

Description: 全数字锁相环ＶＨＤＬ描述并实现功能仿真，另附有图形说明-DPLL VHDL description and achieve functional simulation, followed by graphic shows
Platform: | Size: 286720 | Author: 巢海步 | Hits:

[VHDL-FPGA-Verilog] VHDLDPLL

Description: 比较好的技术文章《基于VHDL的全数字锁相环的设计》有关键部分的源代码。-relatively good technical article, "based on VHDL DPLL the design" a key part of the source code.
Platform: | Size: 167936 | Author: 李湘鲁 | Hits:

[VHDL-FPGA-Verilog] dpll0226

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 184320 | Author: sss | Hits:

[VHDL-FPGA-Verilog] DPLL0227+V+qt6

Description: 用一片CPLD实现数字锁相环,用VHDL或V语言.-with a DPLL CPLD, VHDL or V language.
Platform: | Size: 278528 | Author: sss | Hits:

[Books] changyongmokuai

Description: 智能全数字锁相环的设计用VHDL语言在CPLD上实现串行通信-DPLL intelligent design using VHDL on the CPLD Serial Communication
Platform: | Size: 793600 | Author: 1 | Hits:

[Software Engineering] 200761311574149479

Description: 介绍了如何使用数字锁相环,如何用VHDL实现数字锁相环-on how to use the DPLL, how to use VHDL DPLL
Platform: | Size: 62464 | Author: zhaojia | Hits:

[VHDL-FPGA-Verilog] dpll

Description: ＦＰＧＡ实现全数字锁相环，利用硬件描述评议verilog HDL，顶层文件ＤＰＬＬ．Ｖ-FPGA realization of all-digital phase-locked loop, using hardware description Convocation verilog HDL, the top-level document DPLL. V
Platform: | Size: 4096 | Author: YP | Hits:

[VHDL-FPGA-Verilog] FPGA-DPLL

Description: 基于FPGA实现的一种新型数字锁相环-FPGA-based realization of a new type of digital phase-locked loop
Platform: | Size: 181248 | Author: lixu | Hits:

[Other] DPLL

Description: 一种可编程的全数字锁相环的丝线,可以用来做一个小的课程设计-A programmable DPLL thread can be used to do a small course design
Platform: | Size: 140288 | Author: 国家 | Hits:

[VHDL-FPGA-Verilog] DPLL(VHDL)

Description: 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开-The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
Platform: | Size: 13312 | Author: 国家 | Hits:

[VHDL-FPGA-Verilog] dpll

Description: dpll的verilog代码，完成数字锁相。用于时钟对准，位同步。-dpll the verilog code to complete the digital phase-locked. Alignment for the clock, bit synchronization.
Platform: | Size: 1024 | Author: hsj | Hits:

[Other] DPLL

Description: pll 的数字实现大家支持第一次传-pll digital impliment
Platform: | Size: 49152 | Author: zhangfuquan | Hits:

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[Other resource] VHDLDPLL

[Other resource] 200761311574149479

[VHDL-FPGA-Verilog] pll

[VHDL-FPGA-Verilog] fdpll

[Software Engineering] 010919.pdf

[VHDL-FPGA-Verilog] VHDLDPLL

[VHDL-FPGA-Verilog] dpll0226

[VHDL-FPGA-Verilog] DPLL0227+V+qt6

[Books] changyongmokuai

[Software Engineering] 200761311574149479

[VHDL-FPGA-Verilog] dpll

[VHDL-FPGA-Verilog] FPGA-DPLL

[Other] DPLL

[VHDL-FPGA-Verilog] DPLL(VHDL)

[VHDL-FPGA-Verilog] dpll

[Other] DPLL

[Software Engineering] DPLL

[VHDL-FPGA-Verilog] DPLL

[VHDL-FPGA-Verilog] AD-PLL

[VHDL-FPGA-Verilog] FPGA-based-design-of-DPLL

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