Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - vhdl pipeline

Search list

[VHDL-FPGA-Verilog] pipe

Description: verilog编写的流水线模块-Verilog modules prepared by the Pipeline
Platform: | Size: 5120 | Author: 刘陆陆 | Hits:

[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)

Description: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Platform: | Size: 179200 | Author: 李中伟 | Hits:

[VHDL-FPGA-Verilog] add_3p

Description: 3级流水线，含4元件的22位全加器的VHDL语言实现，适用于altera系列的FPGA-3-stage pipeline, with 4 components of 22 full adder realize the VHDL language, applicable to altera Series FPGA
Platform: | Size: 2048 | Author: wgx | Hits:

[ActiveX/DCOM/ATL] CORDIC_ip

Description: cordic IP core Features Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.v r : Cordic Mode. r = Rotation, v = Vectoring 32 : Precision of the individual vector components. 16 : Precision of the angle. 12 : Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32-cordic IP coreFeatures Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.vr: Cordic Mode. r = Rotation, v = Vectoring 32: Precision of the individual vector components. 16: Precision of the angle. 12: Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32
Platform: | Size: 457728 | Author: abcoabco | Hits:

[Algorithm] multiply

Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed.
Platform: | Size: 4096 | Author: lanty | Hits:

[SCSI-ASPI] dlx_verilog

Description: 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。-This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! That can be downloaded to the FPGA to run commands, instructions can be defined as needed, but also the compiler and the corresponding use, where to learn lines and Verilog friends sharing.
Platform: | Size: 9216 | Author: 李乔 | Hits:

[Software Engineering] VHDLpipeline

Description: 流水线实现圣经，可以大幅度提高系统时钟指标，可以提高编程水平-Pipeline to achieve the Bible, can greatly improve the system clock indicators, can increase the level of programming
Platform: | Size: 147456 | Author: 陈信 | Hits:

[VHDL-FPGA-Verilog] pipeline

Description: 关于FPGA设计中的流水线技巧的使用和例子，一个很好的减少硬件消耗的技巧-About FPGA design using pipelining techniques and examples, a good technique to reduce the hardware consumption
Platform: | Size: 1028096 | Author: JET | Hits:

[VHDL-FPGA-Verilog] DES_IP

Description: 有效的改进3-DES算法的执行速度，采用了多级流水线技术，设计了一种高速的硬件结构，使得原来需要48个时钟周期才能完成的运算，现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中，大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed hardware architecture, making the original 48 clock cycles required to complete the operation, and now only need one clock cycle can be completed. In addition by increasing the input/output control signal. Makes the IP can be easily integrated into the SOC, the SOC has significantly shortened the design cycle.
Platform: | Size: 23552 | Author: charity | Hits:

[VHDL-FPGA-Verilog] float_data_multiple_use_fixed_pipeline_verilog_pro

Description: 采用fpga做小数运算的程序，使用了三级流水线技术，这是学习流水线和定点小数乘法很好的例子！-a program of float multiply, using 3-stage pipeline technology
Platform: | Size: 1024 | Author: xietianjiao | Hits:

[Multimedia program] video

Description: 数字视频信号流水线处理的4个实例： 实例1：产生蓝屏 实例2：产生彩色条测试图像 实例3：叠加移动的物体 实例4：叠加动态视频-Four examples of digital video pipeline
Platform: | Size: 17408 | Author: li nan | Hits:

[Special Effects] H264

Description: h.264(verilog HDL) 这是基于流水线结构的H.264解码器源码-h.264 (verilog HDL) which is based on the pipeline structure of the H.264 decoder source code
Platform: | Size: 99328 | Author: 陈成 | Hits:

[ARM-PowerPC-ColdFire-MIPS] pipeline

Description: 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
Platform: | Size: 3028992 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] 16bit_pipeline

Description: 16 bit pipeline design by vhdl.
Platform: | Size: 318464 | Author: leejp | Hits:

[VHDL-FPGA-Verilog] RISC

Description: 32 bit RISC Processor with 3 stage pipeline
Platform: | Size: 2152448 | Author: rudra | Hits:

[Embeded-SCM Develop] mips

Description: 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
Platform: | Size: 449536 | Author: tong tong | Hits:

[VHDL-FPGA-Verilog] vhdl-pipeline-mips_latest.tar

Description: pipeline mips in vhdl
Platform: | Size: 1137664 | Author: aliakbar | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
Platform: | Size: 2048 | Author: dylan | Hits:

[VHDL-FPGA-Verilog] vhdl-pipeline-mips0

Description: MIPS CPU WITH PIPELINE procesador MIPS-FZA -- Autor: mahdi ahmadi -- Email: mahdi@fza.ir -- mahdifza@yahoo.com -- -- Version: 1.0
Platform: | Size: 23552 | Author: mahdi | Hits:

[VHDL-FPGA-Verilog] vhdl-pipeline-mips_latest

Description: pip-lined MIPS in vhdl
Platform: | Size: 1146880 | Author: sakthivel.p | Hits:
« 12 3 »

CodeBus www.codebus.net