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[Other resource] jop

Description: Java Op Processor java vhdl processor-Java Op java vhdl processor Processor
Platform: | Size: 2789824 | Author: 上面的 | Hits:

[VHDL-FPGA-Verilog] core_arm.tar

Description: 用VHDL语言实现的ARM处理器的标准内核的源代码程序，可在重用-use of the VHDL standard ARM processor core source code procedures, the reuse
Platform: | Size: 655360 | Author: 昭君 | Hits:

[VHDL-FPGA-Verilog] LCD显示实验

Description: ALTERA NIOS处理器，用VHDL在QUARTUS下编写，用NIOS SHELL调试通过，实验LCD液晶显示-Altera NIOS processor, using VHDL in QUARTUS prepared with NIOS SHELL debug through experimental LCD
Platform: | Size: 35840 | Author: xf | Hits:

[VHDL-FPGA-Verilog] SRAM@DMA实验

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Platform: | Size: 33792 | Author: xf | Hits:

[VHDL-FPGA-Verilog] SPI接口音频Codec实验

Description: ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
Platform: | Size: 34816 | Author: xf | Hits:

[Embeded-SCM Develop] memoire_alphabet

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器。实现memory存储。-Altera NIOS processor experiments QUARTUS using VHDL compiler into processors. Achieving memory storage.
Platform: | Size: 1024 | Author: 秦拣俭 | Hits:

[VHDL-FPGA-Verilog] miniMIPS

Description: 这是一个基于mips-I结构的处理器,32bit,冯诺依曼结构-This is based on a MIPS- I structure of the processor, 32bit, von Neumann structure
Platform: | Size: 222208 | Author: tsm998 | Hits:

[VHDL-FPGA-Verilog] Sparc_leon_VHDL

Description: 一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码，但不能保证版图设计ASIC成功 -the Sparc processor (fitted with the United States of the European Space Agency R_tems Embedded operating system) VHDL source code, but it can not guarantee success ASIC Layout
Platform: | Size: 1873920 | Author: 韩红 | Hits:

[SCM] MSP430_i2c

Description: 用C写的I2C总线EEPROM读写程序，在MSP430＋AT24C64～512平台上验证通过。对其他处理器只需简单修改即可使用。-C write I2C EEPROM read and write procedures, the AT24C64 MSP430+ ~ 512 platform validation through. The only other processor can use a simple amendment.
Platform: | Size: 1024 | Author: join | Hits:

[Software Engineering] Designing_a_Multicycle_Processor--en

Description: 介绍怎样利用VHDL语言来实现一个多周期的处理器核心-on how to use VHDL to achieve more than one processor core cycle
Platform: | Size: 64512 | Author: 黎飞飞 | Hits:

[Program doc] ana

Description: 使用VHDL設計一個適用於ETSI OFDM的時間和頻率同步處理器-use of a VHDL design ETSI OFDM applied to the time and frequency synchronization Processor
Platform: | Size: 1404928 | Author: 山姆大叔 | Hits:

[SCM] jop

Description: Java Op Processor java vhdl processor-Java Op java vhdl processor Processor
Platform: | Size: 2789376 | Author: 上面的 | Hits:

[MPI] source

Description: MIPS处理器VHDL代码，实现加法，减法乘除等运算，可综合，-MIPS processor VHDL code, realize adder, subtraction multiplication and division and other operations can be integrated,
Platform: | Size: 6144 | Author: 陈丰 | Hits:

[MPI] MIPS

Description: MIPS处理器的顶层VHDL代码，可综合，可仿真，属硬件描述语言，集成电路设计代码-MIPS processor top-level VHDL code can be integrated to simulation, a hardware description language, integrated circuit design code
Platform: | Size: 1024 | Author: 陈丰 | Hits:

[VHDL-FPGA-Verilog] MultiCycleProcessor

Description: 描述：在D2SB FPGA上的多循环RISK处理器 -Description: D2SB FPGA in the multi-cycle processor RISK
Platform: | Size: 796672 | Author: 陈晓 | Hits:

[VHDL-FPGA-Verilog] LC3-VHDL-another

Description: 另一套LC3 CPU VHDL源码及设计文档，对LC3进行了一些取舍和改造，比如NZP改为NZC，更贴近现实CPU硬件架构。按照ASM进行VHDL编码，更适合数字设计初学者学习。-Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design more suitable for beginners to learn.
Platform: | Size: 808960 | Author: guo | Hits:

[VHDL-FPGA-Verilog] FPGA_FFT

Description: 基于FPGA的高速FFT处理器的设计与实现-FPGA-based high-speed FFT Processor Design and Implementation
Platform: | Size: 73728 | Author: 萧球水 | Hits:

[Editor] processor.tar

Description: i need of vhdl code for 32-bit risc processor
Platform: | Size: 48128 | Author: ganesh | Hits:

[VHDL-FPGA-Verilog] PROCESSOR

Description: PROCESSOR is a design with simple microprocessor implementation.
Platform: | Size: 95232 | Author: leiyu | Hits:

[VHDL-FPGA-Verilog] processor

Description: The purpose of this project is to design a simple Processor Unit
Platform: | Size: 935936 | Author: fahian ahmed | Hits:
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