Search - vhdl processor design

[Program doc] ana

Description: 使用VHDL設計一個適用於ETSI OFDM的時間和頻率同步處理器-use of a VHDL design ETSI OFDM applied to the time and frequency synchronization Processor
Platform: | Size: 1404928 | Author: 山姆大叔 | Hits:

Description: MIPS处理器的顶层VHDL代码，可综合，可仿真，属硬件描述语言，集成电路设计代码-MIPS processor top-level VHDL code can be integrated to simulation, a hardware description language, integrated circuit design code
Platform: | Size: 1024 | Author: 陈丰 | Hits:

[VHDL-FPGA-Verilog] LC3-VHDL-another

Description: 另一套LC3 CPU VHDL源码及设计文档，对LC3进行了一些取舍和改造，比如NZP改为NZC，更贴近现实CPU硬件架构。按照ASM进行VHDL编码，更适合数字设计初学者学习。-Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design more suitable for beginners to learn.
Platform: | Size: 808960 | Author: guo | Hits:

[VHDL-FPGA-Verilog] asdd

Description: 论文基于FPGA的高速实时FFT处理器设计，给出了详细的设计流程！-Thesis of high-speed FPGA-based real-time FFT processor design, detailed design gives the flow!
Platform: | Size: 157696 | Author: 邓振淼 | Hits:

[VHDL-FPGA-Verilog] Pentium

Description: 这两个分别是8位乘法器的VHDL语言的实现，并经过个人用QUARTUS的验证，另外一个是奔腾处理器的设计思想-The two were 8 multiplier realization of VHDL language and personal use Quartus After verification, another is a Pentium processor design idea
Platform: | Size: 378880 | Author: citydremer | Hits:

[VHDL-FPGA-Verilog] FPGA_FFT

Description: 基于FPGA的高速FFT处理器的设计与实现-FPGA-based high-speed FFT Processor Design and Implementation
Platform: | Size: 73728 | Author: 萧球水 | Hits:

[VHDL-FPGA-Verilog] PROCESSOR

Description: PROCESSOR is a design with simple microprocessor implementation.
Platform: | Size: 95232 | Author: leiyu | Hits:

[Software Engineering] Robotic_Exploration_and_Landmark_Determination_us

Description: Sensing and planning are at the core of robot motion. Traditionally, mobile robots have been used for performing various tasks with a general-purpose processor on-board. This book grew out of our research enquiry into alternate architectures for sensor-based robot motion. It describes our research starting early 2002 with the objectives of obtaining a time, space and energy-efficient solution for processing sensor data for various robotic tasks. New algorithms and architectures have been developed for exploration and other aspects of robot motion. The research has also resulted in design and fabrication of an FPGA-based mobile robot equipped with ultrasonic sensors. Numerous experiments with the FPGA-based mobile robot have also been performed and they confirm the efficacy of the alternate architecture.
Platform: | Size: 1348608 | Author: moatasem momtaz | Hits:

[VHDL-FPGA-Verilog] FFTdesign

Description: FFT处理器设计及其应用研究，适合做fpga信号处理的技术人员参考-FFT processor design and applied research, suitable for signal processing fpga technology reference
Platform: | Size: 3174400 | Author: bonjour | Hits:

[VHDL-FPGA-Verilog] 87361039

Description: 于一个8位处理器的分析，和源代码，VHDL语言设计，经过测试-An 8-bit processor in the analysis, and source code, VHDL language design and tested
Platform: | Size: 92160 | Author: hbei | Hits:

[VHDL-FPGA-Verilog] RISC-DSP

Description: RISC-DSP组合处理器设计优化[1].-RISC-DSP processor design portfolio optimization [1].
Platform: | Size: 230400 | Author: 朱伟成 | Hits:

[VHDL-FPGA-Verilog] MAC_Transceiver

Description: MAC(以太网媒体访问控制)是以太网IEEE 802.3协议规定的数据链路层的一部分,使用FPGA替代ASIC,实现以太网MAC功能非常实用。能够实现硬件系统多路多端口的以太网接入,并在自行开发需要以太网接入的嵌入式处理器设计中得到应用。具体探讨以太网MAC的功能定义,使用FPGA实现以太网MAC的方法,对以太网的相关应用设计具有指导作用。 -MAC (Ethernet Media Access Control) is a protocol under the IEEE 802.3 Ethernet data link layer part of the use of FPGA alternative ASIC, Ethernet MAC functionality is very useful. Hardware system to achieve multi-channel multi-port Ethernet access and Ethernet access to its own development needs of embedded processor design has been applied. To specifically explore the functional definition of the Ethernet MAC using FPGA Ethernet MAC method, the design of Ethernet-related applications guide.
Platform: | Size: 1572864 | Author: 陈辉 | Hits:

[Other] cycloneIII_3c120_dev_niosII_standard

Description: 该源码是关于FPGA片上系统sopc的nios处理器设计，他实现了led，lcd以及Internet网络各种功能，源码已经测试通过，读者可以使用-The source is on the FPGA chip on the system sopc the nios processor design, he realized the led, lcd, and Internet networking features, source code has been tested, the reader can use
Platform: | Size: 39700480 | Author: 雪晨 | Hits:

[VHDL-FPGA-Verilog] ahb_ram

Description: AHB接口的ram控制器，可靠性非常强。除了两个周期内发生读到写或写到读的极限情况（一般处理器设计中不会有这种传输方式），其他传输方式完全没有问题-AHB interface ram controller, reliability is very strong. In addition to occurring in two cycles read or write read write the limit (usually processor design will not have such means of transmission), other means of transmission is no problem
Platform: | Size: 1024 | Author: Jasking Wu | Hits:

[Software Engineering] FPGA-cpu

Description: 基于FPGA的简易处理器设计2010/05/04-A simple FPGA-based processor design 2010/05/04
Platform: | Size: 98304 | Author: 阿锦 | Hits:

[Documents] graduated_paper

Description: 基于FPGA的可变点FFT处理器的设计与实现-FPGA-based variable point FFT Processor Design and Implementation
Platform: | Size: 6688768 | Author: 倦怠怪兽 | Hits:

[VHDL-FPGA-Verilog] processor

Description: processor design in vhdl
Platform: | Size: 2048 | Author: vinoth | Hits:

[VHDL-FPGA-Verilog] processor

Description: The purpose of this project is to design a simple Processor Unit
Platform: | Size: 935936 | Author: fahian ahmed | Hits:

[VHDL-FPGA-Verilog] zxcpu

Description: 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a RISC processor with 10 instruction. Assume that main memory can be completed in one cycle is always followed and the CPU read and write operations and the synchronization system uses a main memory unit. 16-bit instruction word processor, including 8 general purpose registers, a 16-bit instruction register and a 16-bit program counter. Processor' s address bus width 16 bits. 16-bit data bus width, fetch and data access are in the hop hoppers data bus. Processor support includes LDA, STA, MOV, MVI, ADD, SUB, AND, OR, JZ, JMP ten instructions. LDA and STA is the only one memory access instructions.
Platform: | Size: 1076224 | Author: zhaoshu | Hits:

[VHDL-FPGA-Verilog] mips-cpu

Description: 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
Platform: | Size: 117760 | Author: 王晓强 | Hits:

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[Program doc] ana

[MPI] MIPS

[VHDL-FPGA-Verilog] LC3-VHDL-another

[VHDL-FPGA-Verilog] asdd

[VHDL-FPGA-Verilog] Pentium

[VHDL-FPGA-Verilog] FPGA_FFT

[VHDL-FPGA-Verilog] PROCESSOR

[Software Engineering] Robotic_Exploration_and_Landmark_Determination_us

[VHDL-FPGA-Verilog] FFTdesign

[VHDL-FPGA-Verilog] 87361039

[VHDL-FPGA-Verilog] RISC-DSP

[VHDL-FPGA-Verilog] MAC_Transceiver

[Other] cycloneIII_3c120_dev_niosII_standard

[VHDL-FPGA-Verilog] ahb_ram

[Software Engineering] FPGA-cpu

[Documents] graduated_paper

[VHDL-FPGA-Verilog] processor

[VHDL-FPGA-Verilog] processor

[VHDL-FPGA-Verilog] zxcpu

[VHDL-FPGA-Verilog] mips-cpu

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