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[Graph program] jpeg_src

Description: 是jpeg标准下图象压缩的vhdl实现工程,包括core文件,测试文件,工程文件-image compression vhdl realization project under standard jpeg.core files, test files and project files are included.
Platform: | Size: 1569792 | Author: 石伟 | Hits:

[Books] VHDL-beststudy

Description: This a set of notes I put together for my Computer Architecture class in 1990. Students had a project in which they had to model a microprocessor architecture of their choice. They used these notes to learn VHDL. The notes cover the VHDL-87 version of the language. Not all of the language is covered (about 95％). You may use this booklet for your own personal learning purposes. You may not use it for profit (eg, selling copies of it, using it in a course for which people pay, etc). If you want to make use of it beyond these conditions, contact me and we can come to some arrangement. -This a set of notes I put together for my Co. mputer Architecture class in 1990. Students ha d a project in which they had to model a microproc essor architecture of their choice. They used t hese notes to learn VHDL. The notes cover the Volume L-87 version of the language. Not all of the lang uage is covered (about 95%). You may use this boo klet for your own personal learning purposes. Y ou may not use it for profit (eg, selling copies of it, using it in a course for which people pay, etc). If you want to make use of it beyond these co nditions. contact me and we can come to some arrangement.
Platform: | Size: 245760 | Author: 罗春晖 | Hits:

[Books] VHDL-book

Description: This is a set of notes I put together for my Computer Architecture class in 1990. Students had a project in which they had to model a microprocessor architecture of their choice. They used these notes to learn VHDL. The notes cover the VHDL-87 version of the language. Not all of the language is covered (about 95％). -This is a set of notes I put together for my Co. mputer Architecture class in 1990. Students ha d a project in which they had to model a microproc essor architecture of their choice. They used t hese notes to learn VHDL. The notes cover the Volume L-87 version of the language. Not all of the lang uage is covered (about 95%).
Platform: | Size: 237568 | Author: 罗春晖 | Hits:

[Embeded-SCM Develop] DDSforsinandcos

Description: 用VHDL实现的DDS，可输出正弦、余弦波形。将所有文件放在一个工程文件里，再分别生存模块，按原理图连接及可-using VHDL DDS, output sine, cosine wave. All documents will be placed on a project document, respectively survival module, according to diagram and can link
Platform: | Size: 7168 | Author: 何明均 | Hits:

[VHDL-FPGA-Verilog] FPGA-based_oscilloscope

Description: FPGA-based_oscilloscope,VHDL写的实现 示波器的程序，及完整的工程描述文档-FPGA-based_oscilloscope. VHDL was oscilloscope to achieve the realization of the process, and complete the project description document
Platform: | Size: 228352 | Author: 严刚 | Hits:

[Linux-Unix] UART

Description: 自己用VHDL写的一个串口程序，调试成功，并且用到了项目中，希望初学者可以借鉴下-Their use VHDL to write a serial program, debug the success of the project and used in the hope that beginners can learn from the next
Platform: | Size: 306176 | Author: yanglei | Hits:

[VHDL-FPGA-Verilog] uart

Description: 串口通讯协议，你您可以自己建个工程，再将需要的VHDL文本，添加到工程中，理解程序在仿真！-Serial communication protocol, you can build your project, and then need VHDL text, added to the project, understand the procedures in the simulation!
Platform: | Size: 10240 | Author: 张亚伟 | Hits:

[USB develop] USB

Description: 这个工程是基于FPGA与Philips的D12 USbB 1.1的完整设计，包括VHDL驱动和主机应用程序及驱动-The project is based on FPGA and Philips of the D12 USbB 1.1 complete design, including VHDL-driven and mainframe applications and drivers
Platform: | Size: 2749440 | Author: Phirix Shaw | Hits:

[Windows Develop] counter24

Description: 24进制计数，可以执行异步复位。该文件包含整个项目-24 hexadecimal counting, can perform asynchronous reset. This document contains the entire project
Platform: | Size: 180224 | Author: iyoung | Hits:

[Other] lcd1602

Description: FPGA工程文件 通过FPGA在LCD上显示“this is my frist program"的字体 已经验证，供大家学习使用。-FPGA through the FPGA project file in the LCD display
Platform: | Size: 630784 | Author: 马亮 | Hits:

[VHDL-FPGA-Verilog] DA_FIR

Description: 基于分布式算法的FPGA实现的FIR滤波器源码，VHDL语言编写的，下载工程文件后可直接在QuartusII7.0上运行。-Based on Distributed algorithms realize the FIR filter FPGA source code, VHDL language, download the project file can be run directly in QuartusII7.0.
Platform: | Size: 531456 | Author: CH | Hits:

[VHDL-FPGA-Verilog] DE2_TV

Description: 这是一个基于DE2平台的工程，适合于初学者学习DE2开发平台的很好的工程，是用Verilog语言编写的-This is a project based on the DE2 platform, suitable for beginners to learn DE2 development platform works well, is to use Verilog language
Platform: | Size: 140288 | Author: wang | Hits:

[VHDL-FPGA-Verilog] traffic_control

Description: 软件开发环境：ISE 7.1i 仿真环境：ISE Simulator 1. 这个实例实现通过ISE Simulator工具实现一个具有两个方向共八个灯的交通灯控制器； 2. 工程在project文件夹中，双击traffic.ise文件打开工程； 3. 源文件在rtl文件夹中，traffic.v为设计文件，traffic_tb.tbw是仿真波形文件； 4. 打开工程后，在工程浏览器中选择traffic_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，进行行为仿真，即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ISE Simulator1. Realize this instance through the ISE Simulator tool to achieve a total of eight lights in both directions of traffic lights controller 2. Works project folder, double-click traffic.ise Open the project document 3. rtl source file in the folder, traffic.v for design documents, traffic_tb.tbw is the simulation waveform files 4. to open a project, the project browser, select traffic_tb.tbw, in the Process View in the double hit
Platform: | Size: 248832 | Author: 李华 | Hits:

[SCM] ADCONTRL0804

Description: 对ad0804的控制工程，编译通过，希望对大家有用-Ad0804 control on the project, the compiler is passed, hope for all of us useful
Platform: | Size: 1928192 | Author: 侯训平 | Hits:

[VHDL-FPGA-Verilog] VHDLjiaotongdeng

Description: 有关毕业设计交通灯的ＶＨＤＬ设计，包括源码程序和仿真图形相关报告。-Traffic lights on the graduation project of VHDL design, including source code and simulation procedures related to the report graphics.
Platform: | Size: 1565696 | Author: 乐乐 | Hits:

[VHDL-FPGA-Verilog] project_UHF_ddc

Description: vhdl语言写的数字下变频的实现，整个工程文件，xlinx ise用的-VHDL language written in the realization of digital down conversion, the whole project file, xlinx ise used
Platform: | Size: 1868800 | Author: 杨斌 | Hits:

[VHDL-FPGA-Verilog] vga_colors

Description: 该项目在VGA显示器上显示8色竖彩条。使用VerilogHDL语言编写，在Altera公司的QuartusII开发环境下验证通过。-The project was displayed on the monitor VGA color vertical color 8. VerilogHDL language used in Altera' s development environment QuartusII verification through.
Platform: | Size: 15360 | Author: submars | Hits:

[Picture Viewer] vga_line

Description: 该项目在VGA显示器上显示一条从屏幕左上角开始，呈135度角的水平线。使用VerilogHDL语言编写，在Altera公司的QuartusII开发环境下验证通过。-The project was displayed on a VGA monitor from the top left corner of the screen to start, showing 135-degree angle of the horizon. VerilogHDL language used in Altera' s development environment QuartusII verification through.
Platform: | Size: 15360 | Author: submars | Hits:

[VHDL-FPGA-Verilog] vga_hex_disp

Description: 该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据，使用ＶｅｒｉｌｏｇＨＤＬ语言编写，在ＱｕａｒｔｕｓＩＩ开发环境下验证。-The Project displays the content of memory cells in the form of hexadecimal numbers. It uses RAM and ROM memory modules available through special functions. This is why before compiling the whole code the user should open mem.v file and change lpm_ram declarations in RAM module and lpm_rom declarations in ROM module into such that are suitable for a particular producer and scheme. There also may appear the necessity of converting .mif files used to memory initialization. The Memory Initialization File is serviced by the Quartus II environment developed by Altera.
Platform: | Size: 18432 | Author: submars | Hits:

[Speech/Voice recognition/combine] ADPCMCodec

Description: Project and source code for ADPCM
Platform: | Size: 717824 | Author: shiva | Hits:
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