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[Other resource] frequency_counter_2(successful)(top-down design).r

Description: 小巧的频率计数器，VHDL源代码和仿真文件具全，直接从管工程文件拷贝过来。绝对可用。-compact frequency counters, VHDL source code and simulation with all documents directly from the control engineering documents copied. Absolutely available.
Platform: | Size: 127107 | Author: wl | Hits:

[Other] VHDL_core_for_1024-point_radix-4_FFT_computation.r

Description: 该论文阐述了用于硬件信号处理的基于4基数12点快速傅立叶变换的VHDL核的设计过程。作者：Vite-Frias Jose Alberto、Romero-Troncoso Rene de Jesus、Ordaz-Moreno
Platform: | Size: 440745 | Author: Rae | Hits:

[VHDL-FPGA-Verilog] 数字电子电路-VGA图像显示控制器

Description: 设计一个VGA图像显示控制器，使其实现以下功能---- 1． 显示模式为640╳480╳60Hz。 2． 用拨码开关控制R，G，B（每个2位），使显示器可以显示64种纯色。 3． 在显示器上显示横向彩条信号（至少六种颜色）。 4． 在显示器上显示纵向彩条信号（至少八种颜色）。 5． 在显示器上显示自行设定的图形，图像等。 6． 选做，自拟其他功能。 所利用到的元器件有： 电脑，显示器，vga接口转换模块， 数字电子电路实验开发板，30Mhz晶振，下载线，电源等
Platform: | Size: 837193 | Author: wangguangchao008@163.com | Hits:

[VHDL-FPGA-Verilog] R-S触发器

Description: R-S触发器的vhdl语言描述
Platform: | Size: 341 | Author: 798291651@qq.com | Hits:

[Documents] 交通灯VHDL

Description: 相关知识 本实验要设计实现一个十字路口的交通灯控制系统，与其他控制系统一样，本系统划分为控制器和受控电路两部分。控制器使整个系统按设定的工作方式交替指挥双方向车辆通行，并接收受控部分的反馈信号，决定其状态转换方向及输出信号，控制整个系统的工作过程。 路*通灯控制系统的有东西路和南北路交通灯 R(红)、Y(黄)、G(绿)三色，所有灯均为高电平点亮。设置20s 的通行时间和5s 转换时间的变模定时电路，用数码管显示剩余时间。提供系统正常工作/复位和紧急情况两种工作模式。
Platform: | Size: 229376 | Author: 157684058@qq.com | Hits:

[VHDL-FPGA-Verilog] VHDL的基本数学运算库

Description: VHDL的基本数学运算库,非常好用-VHDL basic arithmetic library, a very handy! !
Platform: | Size: 232448 | Author: | Hits:

[ISAPI-IE] subr

Description: VHDL 8位无符号除法器 试验报告 计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。 其实现方法是，将除法器分为两个状态：等待状态与运算状态。 开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若不为零则进入运算状态。 -VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it
Platform: | Size: 82944 | Author: aa | Hits:

[VHDL-FPGA-Verilog] frequency_counter_2(successful)(top-down design).r

Description: 小巧的频率计数器，VHDL源代码和仿真文件具全，直接从管工程文件拷贝过来。绝对可用。-compact frequency counters, VHDL source code and simulation with all documents directly from the control engineering documents copied. Absolutely available.
Platform: | Size: 126976 | Author: wl | Hits:

[Books] modelsim_se_tutor

Description: modelsim_se_tutorThis is a set of notes I put together for my Computer Architecture class in 1990. Students had a project in which they had to model a microprocessor architecture of their choice. They used these notes to learn VHDL. The notes cover the VHDL-87 version of the language. Not all of the language is covered (about 95％). -modelsim_se_tutorThis is a set of notes I p ut together for my class Computer Architecture in 1990. Students had a project in which they had to model a microprocessor architecture of thei r choice. They used these notes to learn VHDL. Th e notes cover the VHDL-87 version of the languag e. Not all of the language is covered (about 95%) .
Platform: | Size: 2026496 | Author: 罗春晖 | Hits:

[Education soft system] 000000adada2

Description: 数据结构，二叉树和哈夫曼编码。C++ 1、 学会针对DFA转换图实现相应的高级语言源程序 ·a C++ Class Library of Cr ·简单的防火墙，可以用来学习，作为毕业课设也相当有帮 ·实现ARM 芯片的一对PWM 输出用于控制直流电机 ·Programming the Microsoft ·VC调用java的简单例子。需要注意jvm.dll ·这是介绍在VC++6。0下如何编写GPIB程序。有 ·GPS坐标转换软件：直角坐标与大地坐标转换 ·我的一个同学写的毕业论文 希望对大家来说是有用的 ·最简单的用工作线程控制有进程条的窗口,主窗口调用后 ·VC数据库编程综合应用。订单的管理 ·vhdl,用i2c控制philips的7111和7 ·基于winsock2的网络封包截获技术,源代码清楚 -data structure, binary tree and Huffman coding. C 1. Society against DFA conversion map corresponding high-level language source of a Class C of C Library r simple firewall can be used to study, as part of the graduation class is fairly established to help achieve the ARM chip of a PWM output for controlling Motor Prog ramming the Microsoft VC called java simple example. This needs attention jvm.dll is introduced in VC 6. 0 GPIB preparation procedures. Have GPS coordinates conversion software : Cartesian coordinates of the earth and converting one of my classmates wrote the dissertation hope for all of us is the most useful simple Working with a thread control of the process window, the main window after calling VC Database Programming integrated application. Vhdl orders management, i2c co
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] baseball

Description: 用VHDL开发的棒球游戏，可以在QuartusII环境下编译，适用于各种FPGA开发板。-VHDL development of the baseball game, in QuartusII environment compiler, apply to all FPGA development board.
Platform: | Size: 56320 | Author: zhang | Hits:

[Other] VHDL_core_for_1024-point_radix-4_FFT_computation.r

Description: 该论文阐述了用于硬件信号处理的基于4基数12点快速傅立叶变换的VHDL核的设计过程。作者：Vite-Frias Jose Alberto、Romero-Troncoso Rene de Jesus、Ordaz-Moreno -The paper described the hardware for signal processing based on the 4 base 12 points Fast Fourier Transform Nuclear VHDL design process. Authors: Vite-Frias Jose Alberto, Romero-Troncoso Rene de Jesus, Ordaz-Moreno
Platform: | Size: 440320 | Author: Rae | Hits:

[VHDL-FPGA-Verilog] BasicRSA

Description: RSA加密算法的VHDL实现，通过实际FPGA验证。-RSA encryption algorithm of VHDL realize, through actual FPGA verification.
Platform: | Size: 9216 | Author: 张开文 | Hits:

[ActiveX/DCOM/ATL] CORDIC_ip

Description: cordic IP core Features Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.v r : Cordic Mode. r = Rotation, v = Vectoring 32 : Precision of the individual vector components. 16 : Precision of the angle. 12 : Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32-cordic IP coreFeatures Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.vr: Cordic Mode. r = Rotation, v = Vectoring 32: Precision of the individual vector components. 16: Precision of the angle. 12: Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32
Platform: | Size: 457728 | Author: abcoabco | Hits:

[SCM] light

Description: A方向和B方向各设红（R）、黄（Y）、绿（G）和左拐（L）4盏灯，4种灯按合理的顺序亮灭，并将时间以倒计时的形式显示出来。同时要设置两个方向的紧急通道模式，当某一方向有紧急事件发生时，交警按下紧急通道按钮，该方向绿灯亮，另外一个方向红灯亮，等紧急事件解除后（假定计时10s）,交通恢复原来的状态 要求在数码管上显示两个方向的灯种和计时，实现紧急情况按钮输入功能 根据交通灯控制要实现的功能，可考虑用两个并行执行的always模块（两个进程）来分别控制A和B两个方向的4盏灯。这两个always模块使用同一个时钟信号，以进行同步，也就是说，两个进程的敏感信号时同一个 每个always模块控制一个方向的4种灯按如下顺序点亮，并往复循环：绿灯－黄灯－左拐灯－黄灯－红灯，灯亮的时间由自己设定 由于板上资源有限，如觉得实现困难，可去掉左拐灯，即顺序为绿灯－黄灯－红灯。-err
Platform: | Size: 603136 | Author: 张星 | Hits:

[VHDL-FPGA-Verilog] VHDL-ROM4

Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成 2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。 3.将50MHz作为输入时钟。 -ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input.
Platform: | Size: 98304 | Author: 宫逢源 | Hits:

[VHDL-FPGA-Verilog] Thecontrolofsteppermotorandservomotorbasedonvhdl.r

Description: 本程序采用vhdl语言对步进电机及伺服电机进行控制，控制方式灵活，有变速，正反转，显示等多个模块-This procedure using VHDL language of stepper motor and servo motor control, control flexibility, have variable speed, positive, showing a number of modules, etc.
Platform: | Size: 4096 | Author: 阿汤 | Hits:

[Other] 43680517vhdl_design_representation_and_synthesis.r

Description: vhdl 表示和综合，是一本很好的教材，是国外经典的教材-vhdl expressed and integrated, is a very good teaching is the teaching of foreign classics
Platform: | Size: 19243008 | Author: jiangpeng | Hits:

[VHDL-FPGA-Verilog] vhdl-2008-just-the-new-stuff-systems-on-silicon.r

Description: VHDL is defined by IEEE Standard 1076, IEEE Standard VHDL Language Reference Manual (the VHDL LRM). The original standard was approved in 1987. IEEE procedures require that standards be periodically reviewed and either reaffirmed or revised. The VHDL standard was revised in 1993, 2000, and 2002. In each revision, new language features were added and some existing features enhanced. The aim in each revision was to improve the language as a tool for design and verification of digital systems. Since the 2002 revision, there have two parallel efforts to further develop the language. The first was the VHDL Procedural Interface (VHPI) Task Force, a subcommittee of the IEEE P1076 Working Group. The VHPI Task Force prepared an interim amendment to the standard, formally approved by IEEE in March 2007. The amendment is titled IEEE 1076c, Standard VHDL Language Reference Manual—Amendment 1: Procedural Language Application Interface.
Platform: | Size: 800768 | Author: chane | Hits:

[VHDL-FPGA-Verilog] 3813412-Matlab-Simulink-Simulink-Matlab-to-Vhdl.r

Description: Simulink/Matlab-to-VHDL Route for Full-Custom/FPGA Rapid Prototyping of DSP Algorithms
Platform: | Size: 147456 | Author: T. H. Sutikno | Hits:
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