Search - vhdl using encoder

[Applications] RS encoder(Verilog)

Description: RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
Platform: | Size: 5120 | Author: 王锋 | Hits:

[EditBox] enc

Description: HDB3编码器使用VHDL编制对于基带传输很有用的程序-HDB3 encoder using VHDL preparation for baseband transmission useful procedure
Platform: | Size: 1024 | Author: ls | Hits:

[Communication] BCH_bm_simulation

Description: An encoder/decoder for binary BCH codes Error correction using the BERLEKAMP-MASSEY ALGORITHM.Any (valid) code length can be input-An encoder/decoder for binary BCH codes Er Ryan correction using the BERLEKAMP- MASSEY ALG ORITHM.Any (valid) code length can be input
Platform: | Size: 5120 | Author: 里海 | Hits:

[VHDL-FPGA-Verilog] DCT

Description: 用verilog语言实现DCT编解码附有DCT的说明-Using Verilog language realize DCT codec with a description of DCT
Platform: | Size: 65536 | Author: 周韧研 | Hits:

[VHDL-FPGA-Verilog] mancheester_v

Description: 用Verilog HDL实现的曼彻斯特编码器和解码器。-Using Verilog HDL realize the Manchester encoder and decoder.
Platform: | Size: 9216 | Author: wangyunshann | Hits:

[Compress-Decompress algrithms] rs_encoder

Description: 一个很不错RS编码，用于DVB的信道编码，用VHDL语言编写，在FPGA上通过验证。-A very good RS encoder for DVB Channel Coding using VHDL language, in the FPGA-validated.
Platform: | Size: 3072 | Author: 杨宇 | Hits:

[Special Effects] video_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[VHDL-FPGA-Verilog] HDB3encoder

Description: 数字基带信号的传输是数字通信系统的重要组成部分。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。采用AMI码的信号交替反转，有可能出现四连零现象，这不利于接收端的定时信号提取。而HDB3码因其无直流成份、低频成份少和连0个数最多不超过三个等特点，而对定时信号的恢复十分有利，并已成为CCITT协会推荐使用的基带传输码型之一。为此，本文利用VHDL语言对数据传输系统中的HDB3编码器进行了设计。-Digital baseband signal transmission is an important digital communication system components. In digital communications, some occasions may, after modulation and demodulation process, and on the base-band signals transmitted directly. AMI code using the turn signal inversion, there may be zero Silian phenomenon, which is not conducive to the receiving end of the timing signal extraction. HDB3 code and its non-DC components, and even less low-frequency components of 0 up to more than three the number of characteristics such as timing signals for the recovery of very favorable, and the Association has become the CCITT recommended base-band transmission-type, one code. In this paper, the use of VHDL language in the data transmission system HDB3 encoder has been designed.
Platform: | Size: 108544 | Author: shashou | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: Very high speed integrated Hardware Description Language (VHDL) -是IEEE,工业标准硬件描述语言 -用语言的方式而非图形等方式描述硬件电路容易修改容易保存 -特别适合于设计的电路有: 复杂组合逻辑电路,如: -译码器,编码器,加减法器,多路选择器,地址译码 -Very high speed integrated Hardware Description Language (VHDL)- is the IEEE, industry-standard hardware description language- rather than using language to describe graphics hardware, such as easy to modify the circuit easier to save- is particularly suited to the design of the circuit are: the complexity of combinational logic circuits, such as:- Decoder, encoder, plus or minus objects, MUX, address decoding
Platform: | Size: 1735680 | Author: sherry | Hits:

[File Format] 17bit_Smart_Absolute_Encoder

Description: 多摩川17bit绝对值编码器的NRG协议文档，配合上传的解码源程序，采用半双工的通信模式。-Tamagawa 17bit absolute encoder NRG agreement documents, with the upload source decoder, using half-duplex communication mode.
Platform: | Size: 4419584 | Author: 王中超 | Hits:

[Communication] conv_vhdl

Description: 用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
Platform: | Size: 1024 | Author: 吴雪 | Hits:

[VHDL-FPGA-Verilog] encoderdecoder

Description: this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural
Platform: | Size: 142336 | Author: jatab | Hits:

[Software Engineering] encoder

Description: 此为介绍一光电编码器的学术论文，采用VHDL语言编写，介绍了4分频的实现。-This is the description of the papers of a photoelectric encoder using VHDL language, introduced a 4-band implementation.
Platform: | Size: 108544 | Author: name | Hits:

[VHDL-FPGA-Verilog] Altera_IP_verilog

Description: Altera IP的产生与实现。定制一个8B10B编码器，采用verilog语言建立仿真模型，并验证。-Altera IP generation and implementation. Customize a 8B10B encoder, using verilog language, a simulation model, and verify.
Platform: | Size: 395264 | Author: Gorce | Hits:

[VHDL-FPGA-Verilog] encoder

Description: 802.11a卷积码的实现，使用公式133和177，可以用标准viterbi解码-802.11a convolutional code to achieve, using the formula 133 and 177, you can use standard viterbi decoding
Platform: | Size: 1024 | Author: Team | Hits:

[VHDL-FPGA-Verilog] 3Channel_CIS_Processor_with-VHDL.ZIP

Description: This usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting -This is usefull source for control CIS Sensor and has fallowed functions 1) Read image data frome 3channel 200dpi CIS Sensor 2)Encoder Sync Technoledge for more high resolution analiysys with shared the time divition 3)Psudo Video Ram Read by using Xilinx BRAM 4)MCU Bidirectioal data Transfer 5) ADC data Converting
Platform: | Size: 15360 | Author: jeong | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Applications] RS encoder(Verilog)

[EditBox] enc

[Communication] BCH_bm_simulation

[VHDL-FPGA-Verilog] DCT

[VHDL-FPGA-Verilog] mancheester_v

[Compress-Decompress algrithms] rs_encoder

[Special Effects] video_process_base_on_DSPandFPGA

[VHDL-FPGA-Verilog] HDB3encoder

[VHDL-FPGA-Verilog] vhdl

[File Format] 17bit_Smart_Absolute_Encoder

[Communication] conv_vhdl

[VHDL-FPGA-Verilog] encoderdecoder

[Software Engineering] encoder

[VHDL-FPGA-Verilog] Altera_IP_verilog

[VHDL-FPGA-Verilog] encoder

[VHDL-FPGA-Verilog] 3Channel_CIS_Processor_with-VHDL.ZIP

[VHDL-FPGA-Verilog] Priority-encoder

[VHDL-FPGA-Verilog] encoder

[VHDL-FPGA-Verilog] 7segment-display-VHDL

[VHDL-FPGA-Verilog] VHDL-code

CodeBus www.codebus.net