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[Program doc] Xilinx ISE 使用入门手册.doc

Description: Xilinx ISE 使用入门手册.doc
Platform: | Size: 1509888 | Author: panqihe | Hits:

[Program doc] xilinx ISE 10.1 使用教程.doc

Description: xilinx ISE 10.1 使用教程.doc
Platform: | Size: 743936 | Author: panqihe | Hits:

[Program doc] VHDL上机手册(基于Xilinx ISE & ModelSim).doc

Description: VHDL上机手册(基于Xilinx ISE & ModelSim).doc
Platform: | Size: 730112 | Author: panqihe | Hits:

[VHDL-FPGA-Verilog] xilinx_doc

Description: 一本介绍如何使用xilinx的好书，分享给大家-Describes how to use a xilinx books, share to everybody
Platform: | Size: 6767616 | Author: wyq | Hits:

[VHDL-FPGA-Verilog] xapp856

Description: 基于FPGA的SFI接口实现（VHDL，Verilog and doc）-SFI-4.1 16-Channel SDR Interface with Bus Alignment
Platform: | Size: 556032 | Author: wicky | Hits:

[VHDL-FPGA-Verilog] xapp283

Description: YUV到RGB的色彩空间转换器(VHDL,Verilog and doc)-Color Space Converter: Y’CrCb to R’G’B’
Platform: | Size: 175104 | Author: wicky | Hits:

[VHDL-FPGA-Verilog] xapp622

Description: 644 MHz SDR LVDS 发射器/接收器(verilog and doc)-644-MHz SDR LVDS Transmitter/Receiver
Platform: | Size: 355328 | Author: wicky | Hits:

[VHDL-FPGA-Verilog] Xilinx_MicroBlaze

Description: 手把手学习xilinx的microblaze的使用方法，doc文档，希望对大家有帮助-Hands-on learning to use xilinx the microblaze, doc documents, we want to help
Platform: | Size: 5120 | Author: veskel | Hits:

[VHDL-FPGA-Verilog] I2C_control

Description: Xilinx提供的I2C控制器代码,Master/Slave全功能- Readme File for I2C Customer Pack Created: 7/8/99 ALS Revised: 11/4/99 ALS ******************************************************************************************************************************************** ******************************************************************************************************************************************** File Contents ******************************************************************************************************************************************** This zip file contains the following folders: \doc -- Document for the CoolRunner I2C Controller. \exemplar -- Exemplar synthesis files. This design was synthesized using Exemplar and the resulting EDIF file imported into XPLA Professional V3.22 \vhdl_source -- Source VHDL files: i2c.vhd - top level file i2c_control.vhd - control function for the I2C master/slave shift.vhd - shift register uc_interface.vhd- uC interface f
Platform: | Size: 150528 | Author: leon | Hits:

[Software Engineering] xapp283

Description: YUV to RGB coversion doc from Xilinx.
Platform: | Size: 67584 | Author: Amit Saini | Hits:

[Software Engineering] xapp637

Description: Extended YUV to RGB conversion doc from Xilinx
Platform: | Size: 61440 | Author: Amit Saini | Hits:

[Other] yuv_rgb

Description: Extended YUV to RGB conversion doc from Xilinx
Platform: | Size: 1024 | Author: Amit Saini | Hits:

[Software Engineering] ise_how_to_work

Description: ise 工作 各个 步骤 详细 解释 ----原创.doc xilinx 各个 软件，如何执行-ise explain in detail all the steps of---- original doc xilinx software, how to perform
Platform: | Size: 188416 | Author: 王一凡 | Hits:

[VHDL-FPGA-Verilog] VGA.doc

Description: 用vhdl实现横竖彩条纹的显示，通过xilinx仿真软件生成bit文件，下载到fpga开发板上-Horizontal and vertical stripes using vhdl color display, generate bit file by xilinx simulation software, download it to fpga development board
Platform: | Size: 8192 | Author: sandy | Hits:

[VHDL-FPGA-Verilog] project-main-doc

Description: The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be compress .In this project it is possible to reduce the input data. To compress the original input data or to reduce the input data it will never effect the original information and it is possible to consume less power for data transmission. It is possible to transmit the data efficiently by using these methods here two compression methods are there. 1) Lossless compression and 2) Lossy compression method. In this project to compress the input data by using lossless compression technique. To this project by using Xilinx 9.1i simulator and to write the code by using VHDL module-The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be compress .In this project it is possible to reduce the input data. To compress the original input data or to reduce the input data it will never effect the original information and it is possible to consume less power for data transmission. It is possible to transmit the data efficiently by using these methods here two compression methods are there. 1) Lossless compression and 2) Lossy compression method. In this project to compress the input data by using lossless compression technique. To this project by using Xilinx 9.1i simulator and to write the code by using VHDL module
Platform: | Size: 207872 | Author: gowtham | Hits:

[VHDL-FPGA-Verilog] 可逆计数器VHDL描述

Description: 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4，利用Xilinx ISE软件，利用VHDL软件编写可逆计数器，包含实验说明以及代码实现VHDL.doc文件,UCF管脚绑定文件(In the FPGA:Spartan-3E development board series, XC3S500E, package: FGT320, speed -4, using Xilinx ISE software, written in a reversible counter by using VHDL software, including experimental description and code to achieve the VHDL.doc file, the UCF pin binding file)
Platform: | Size: 12288 | Author: lixilin | Hits:

[VHDL-FPGA-Verilog] 按键去抖电路VHDL描述

Description: 在开发板FPGA：Spartan-3E 系列，型号：XC3S500E，封装：FGT320，速度-4，利用Xilinx ISE软件，利用VHDL软件编写按键去抖电路，包含实验说明以及代码实现VHDL.doc文件,UCF管脚绑定文件(In the FPGA:Spartan-3E development board series, XC3S500E, package: FGT320, speed -4, using Xilinx ISE software, write the debounce circuit by using VHDL software, including experimental description and code to achieve the VHDL.doc file, the UCF pin binding file)
Platform: | Size: 29696 | Author: lixilin | Hits:

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