Search - xilinx ip

[Consulting and training] XILINX全系列产品选型速查指南

Description: 包括XILINX的FPGA、CPLD、IP、工具、开发板等
Platform: | Size: 404947 | Author: zheng_wb@sina.com | Hits:

[Mathimatics-Numerical algorithms] 81i_radix2_xfft1024_v3_2

Description: xilinx FFT using ip core project navigator-xilinx ip using FFT core project navigator
Platform: | Size: 1432576 | Author: ningchang | Hits:

[VHDL-FPGA-Verilog] pci144_vhdl

Description: PCI vhdl for Fpga designer to design PCI IP
Platform: | Size: 3072 | Author: 李晓媛 | Hits:

[Other] lab2mb

Description: 为硬件设计添加 IP，这个实验将使用 Xilinx 开发平台工作室（XPS）为一个已有的处理器系统添加附加 IP（硬件功能单元）。你将会学习通过IP目录图标添加附加IP。在实验的最后，你将会创建设计的网络清单，并使用 ISE 来实现设计。-For the hardware design to add IP, this experiment will use the Xilinx Platform Studio (XPS) for an existing system processor to add additional IP (hardware functional unit). You will be learning through the IP catalog icons to add additional IP. Finally in the experiment, you will create the design of network inventory and to use ISE design.
Platform: | Size: 1482752 | Author: jie | Hits:

[VHDL-FPGA-Verilog] vhdl_source

Description: MP3 for XPLA3 XILINX.CPLD,必须在XILINX的FPGA芯片下使用,因为IP核是xilinx-MP3 for XPLA3 XILINX.CPLD, must XILINX use of FPGA chip, as is the Xilinx IP core
Platform: | Size: 64512 | Author: sq | Hits:

[VHDL-FPGA-Verilog] studyFFTcore

Description: 调用FPGA的IP核实现FFT运算，在xilinx的vertex4sx55FPGA的实现-Call FPGA implementation of the IP core FFT computation, in the Xilinx implementation of the vertex4sx55FPGA
Platform: | Size: 1287168 | Author: 徐成发 | Hits:

[VHDL-FPGA-Verilog] pci_core.tar

Description: vhdl 写的 PCI IP核程序，已经过测试-pci ip core
Platform: | Size: 23552 | Author: planet1997 | Hits:

[Documents] 08Tutorial3

Description: tutorial of xilinx ip core
Platform: | Size: 376832 | Author: adeel | Hits:

[VHDL-FPGA-Verilog] OpenCorespcicore

Description: PCI IP核功能实现，符合V2.2协议-realize pci function
Platform: | Size: 1203200 | Author: sophie | Hits:

[VHDL-FPGA-Verilog] lcd_drv

Description: IP core for LCD controller of Xilinx FPGA
Platform: | Size: 2048 | Author: phong duong | Hits:

[VHDL-FPGA-Verilog] sdram_ver_134

Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is based Xilinx FPGA Playform.
Platform: | Size: 108544 | Author: peace | Hits:

[Books] Block_Memory_Generator_v3.3

Description: Xilinx IP core 生成手册-Block_Memory_Generator
Platform: | Size: 1935360 | Author: wang pu | Hits:

[VHDL-FPGA-Verilog] blk_write

Description: verilog 块ram写入操作 fpga xilinx ip core-Verilog block_ram module fpga xilinx ip core
Platform: | Size: 2048 | Author: y_gt | Hits:

[VHDL-FPGA-Verilog] pn2212

Description: Xilinx IP核DPD的产品说明，全英文文档，下载前需注意；-product notes of Xilinx ip core DPD
Platform: | Size: 1247232 | Author: philoman | Hits:

[VHDL-FPGA-Verilog] ISE_lab17

Description: 本实验使用 XILINX 提供的IP 核，并例化该IP 核来实现正弦信号发生器的功能。由于 ISE 中有DDS（Direct Digital Synthesizer 5.0）IP 核，因此只需要编写一个顶层文件来调用 Core Generator 生成的IP 即可。-This study provides the IP core using the XILINX, and cases of the IP core to achieve the sinusoidal signal generator functions. ISE in the DDS (Direct Digital Synthesizer 5.0) IP core, so only need to write a top-level file to call the IP Core Generator can generate.
Platform: | Size: 4096 | Author: | Hits:

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