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The physical layer control of MAC network control (VHDL)
Update : 2025-03-04 Size : 8kb Publisher : 卢生

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Based on Altera's IP core, to complete the serial transceiver, as well as custom IP, as a custom AXI bus interface example
Update : 2025-03-04 Size : 18.87mb Publisher : 机智的伟哥哥

this is ptp,this is ptp this is ptp this is ptp
Update : 2025-03-04 Size : 9.33mb Publisher : 小龙1356

Downloaded:0
code to enhance a picture in verilog.
Update : 2025-03-04 Size : 1.7mb Publisher : nishusingla

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code to perform thresholding operation on a picture
Update : 2025-03-04 Size : 3.96mb Publisher : nishusingla

Downloaded:0
code to perform brightness operation
Update : 2025-03-04 Size : 1.81mb Publisher : nishusingla

Downloaded:0
code for inverting an image in verilog
Update : 2025-03-04 Size : 31kb Publisher : nishusingla

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code for "booth multiplier" using verilog
Update : 2025-03-04 Size : 580kb Publisher : nishusingla

Downloaded:0
example 0xB0A2 offset=(0xB0-0xA1)*(141*12)+(0xA2-0xA1)*12/8 mod 4 bin[offset+ 0*141].D3..D0 bin[offset+ 0*141+1].D7..D0 bin[offset+ 1*141].D3..D0 bin[offset+ 1*141+1].D7..D0 bin[offset+ 2*141].D3..D0 bin[offset+ 2*141+1]
Update : 2025-03-04 Size : 1.38mb Publisher : 李军飞

Downloaded:0
filtre de sobel sur fpga
Update : 2025-03-04 Size : 197kb Publisher : jordra

DE2_70_D5M_LTM_sobel_dilation
Update : 2025-03-04 Size : 243kb Publisher : jordra

Downloaded:0
DE2_70 sobel_dilationdsd
Update : 2025-03-04 Size : 232kb Publisher : jordra
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