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VHDL-FPGA-Verilog list
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A comprehensive Verilog Grammar (University of Cambridge, photocopy).
Update : 2024-12-28 Size : 292kb Publisher : Vincent、

Verilog beginner's learning experience. Suitable for rookie.
Update : 2024-12-28 Size : 505kb Publisher : Vincent、

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The algorithm is: X^16+X^12+X^5 The simulation verification passed, very good, you can use it to try it.
Update : 2024-12-28 Size : 9.64mb Publisher : 夏日的焰火

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VGA synchronization using Altera Cyclone II
Update : 2024-12-28 Size : 377kb Publisher : godup

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Simple finite state machine on Altera Cyclone II
Update : 2024-12-28 Size : 284kb Publisher : godup

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A simple ALU on Altera FPGA for learners
Update : 2024-12-28 Size : 359kb Publisher : godup

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The digital clock is designed with VHDL. Optional 24h and 12h two kinds of time system, apply to the button to shake.
Update : 2024-12-28 Size : 20kb Publisher : redsoul丶

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build ofdm system transceiver
Update : 2024-12-28 Size : 133kb Publisher : zizimaghraby

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A digital clock, ring lasts for two seconds per minute
Update : 2024-12-28 Size : 6.96mb Publisher : 张小憨

Verilog Course Peking University
Update : 2024-12-28 Size : 1.21mb Publisher : LiangJN

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gal program loader for windows with description for galblaster board
Update : 2024-12-28 Size : 518kb Publisher : mbuczek

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complete fpga VHDL code for VGA display
Update : 2024-12-28 Size : 177kb Publisher : sofa
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