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VHDL-FPGA-Verilog list
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spanning tree adder writtern vHDL Code
Update : 2024-12-28 Size : 185kb Publisher : GIRISH

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carry_select_adder for 16-bit in verilog
Update : 2024-12-28 Size : 2kb Publisher : GIRISH

Asynchronous FIFO Architectures Vijay A. Nebhrajani
Update : 2024-12-28 Size : 196kb Publisher : 啸傲.

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Using verilog language, LED lights on the FPGA development version
Update : 2024-12-28 Size : 178kb Publisher : wz2016520157

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Phase-locked loop with FPGA to achieve frequency division, the frequency of the reference clock through the PLL core frequency to generate a variety of clock generation.
Update : 2024-12-28 Size : 230kb Publisher : 棋墨黑白

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ADDA debugger routines with black gold FPGA, and learn together with everyone to learn progress, mainly about the debug of 8 ADDA.
Update : 2024-12-28 Size : 4.21mb Publisher : 棋墨黑白

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Using FPGA to debug UART in parallel, make comparison with the way of MCU debugging
Update : 2024-12-28 Size : 352kb Publisher : 棋墨黑白

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Explain Xilinx Spartant_6 Series FPGA ROM IP core debugging process, for your reference learning
Update : 2024-12-28 Size : 4.04mb Publisher : 棋墨黑白

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The function of timing and countdown of the stopwatch based on VHDL language.
Update : 2024-12-28 Size : 436kb Publisher : 水盼

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Implement vga using verilog,which is including the text contents.
Update : 2024-12-28 Size : 2.31mb Publisher : 缘木

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This zip contains an AT24C02 IIC interface, which can read from 24c02 and write data into it.
Update : 2024-12-28 Size : 7.14mb Publisher : 蝠蝙

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This zip file contains a quartus ii project, which can driven the LED screen LCD5110.
Update : 2024-12-28 Size : 4.51mb Publisher : 蝠蝙
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