VHDL-FPGA-Verilog List Page 105

VHDL-FPGA-Verilog list

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sdr_sdram Downloaded：0: sdram verilog. SDRAM using interface simulation, Altera company IP use method
Update : 2024-12-29 Size : 12kb Publisher : 风雪来
DACAD9708 Downloaded：0: DAC_AD9708 verilog HDL code, AD9708 for top file, need to configure read only memory, output sine wave.
Update : 2024-12-29 Size : 3kb Publisher : w74177
led Downloaded：0: A flow light program for FPGA.
Update : 2024-12-29 Size : 3.05mb Publisher : Y_pricipal
02_run_flash_led Downloaded：0: FPGA burn program to flash engineering example, the chip signal is EP4CE6F17C8N
Update : 2024-12-29 Size : 5.18mb Publisher : Y_pricipal
03_key_detect_1 Downloaded：0: FPGA development board key process, the chip model is EP4CE6F17C8N
Update : 2024-12-29 Size : 5.11mb Publisher : Y_pricipal
04_key_detect_2 Downloaded：0: FPGA development board key process, the chip model is EP4CE6F17C8N
Update : 2024-12-29 Size : 5.13mb Publisher : Y_pricipal
09_vga Downloaded：0: FPGAvga's use example, the chip model is EP4CE6F17C8N
Update : 2024-12-29 Size : 27.38mb Publisher : Y_pricipal
spi_master Downloaded：0: The read and write erasure commands of the serial flash communicate through the SPI interface. The CPU chip communicates with the FPGA through the SPI interface. Other functional integrated circuit chip parameters regist
Update : 2024-12-29 Size : 3.23mb Publisher : 小云子
frequency Downloaded：0: It is used in FPGA development, written in VERILOG language, and simulated on the QUARTUS II simulation platform to realize the function of the frequency meter.
Update : 2024-12-29 Size : 363kb Publisher : 丶静俟
HDB3 Downloaded：0: In accordance with the requirements of the logical analysis of the design and modeling of the digital baseband signal HDB3 decoder, HDB3 decoder principle, understand the logic function of each module circuit diagram, co
Update : 2024-12-29 Size : 8.57mb Publisher : Remrinrin
VGA显示8色彩条和方格 Downloaded：0: sdfdsssadadadsadadasdadad
Update : 2024-12-29 Size : 3.17mb Publisher : Dragonl
5L_SVPWM_ANPC_CPLD Downloaded：0: Five level SVPWM pulse trigger program based on CPLD hardware description language
Update : 2024-12-29 Size : 327kb Publisher : hurui

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