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VHDL-FPGA-Verilog list
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Booth multiplier to implement the common Booth multiplication algorithm
Update : 2025-02-26 Size : 323kb Publisher : 深蓝浅蓝eva

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pll reconfig xilinx vivado
Update : 2025-02-26 Size : 17kb Publisher : 没法注册

Conversion of binary code into BCD code source program
Update : 2025-02-26 Size : 10kb Publisher : zhanglei123456

Conversion of BCD code into seven segment code source program
Update : 2025-02-26 Size : 9kb Publisher : zhanglei123456

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VHDL source code of IIc time series logic, easy to debug time series
Update : 2025-02-26 Size : 11kb Publisher : zhanglei123456

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Instructions for programming on MaxplusII_Alter
Update : 2025-02-26 Size : 4.27mb Publisher : zhanglei123456

this is code for carry_select adder_16-bit. written in verilog.
Update : 2018-01-12 Size : 743byte Publisher : spgp1306

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Router 8-bit fifo design, written in Verilog
Update : 2018-01-12 Size : 822byte Publisher : spgp1306

Image processing binarisation verilog code
Update : 2018-01-12 Size : 308byte Publisher : spgp1306

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Basic Verilog code includes RING and Johnson counters, Up-down counters, RAM, ROM, SIPO, PISO, SISO, PIPO, Mealy and Moore FSM codes
Update : 2018-01-12 Size : 9.17kb Publisher : spgp1306

Generic kogge-stone adder and testbench IN VHDL
Update : 2018-01-12 Size : 218.36kb Publisher : spgp1306

27-bit spanning tree adder written in VHDL coding
Update : 2018-01-12 Size : 185.53kb Publisher : spgp1306
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