VHDL-FPGA-Verilog List Page 246

VHDL-FPGA-Verilog list

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DE2_Basic_Computer Downloaded：0: Convert DE2 FPGA to Small Computer
Update : 2025-01-13 Size : 1.2mb Publisher : frozeus
mmp Downloaded：0: Electronic puzzle lock
Update : 2025-01-13 Size : 692kb Publisher : ZZZqqq
asyn_fifo Downloaded：0: The source package is asynchronous FIFO Verilog language model, including 2 main parts: asynchronous FIFO control module, test files.
Update : 2025-01-13 Size : 1kb Publisher : 叶古
syn_fifo Downloaded：0: The source package is a synchronous FIFO Verilog language model, including 2 main parts: synchronous FIFO control module, test files.
Update : 2025-01-13 Size : 1kb Publisher : 叶古
Estacionamento Downloaded：0: code of a system park, check out
Update : 2025-01-13 Size : 29kb Publisher : nome
test Downloaded：0: Sine wave can be generated through the ROM, the document has complete code, you can download directly
Update : 2025-01-13 Size : 3.42mb Publisher : 哈虎
Nios2_LB0 Downloaded：0: Use the Nios platform to run the LED cycle with the C language
Update : 2025-01-13 Size : 21.27mb Publisher : 大头q
code Downloaded：0: Realize CNN network using HLS tool
Update : 2025-01-13 Size : 9kb Publisher : 蔡宇杰
BCH_VLSI Downloaded：0: BCH Encoder realized using HLS tool. Combinational logic.
Update : 2025-01-13 Size : 13.83mb Publisher : 蔡宇杰
tdc-core-master Downloaded：0: The HDL implementation of TDC function, verified in spartan 6 platform.
Update : 2025-01-13 Size : 984kb Publisher : dragonxu
decoder3_8 Downloaded：0: an decoder 3 to 8 with switch
Update : 2025-01-13 Size : 4.08mb Publisher : jingcuz
uart2bus_latest.tar Downloaded：0: uart sdadasdsadasdasdasda
Update : 2025-01-13 Size : 244kb Publisher : jiannanc

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