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VHDL-FPGA-Verilog list
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MUT32 pipelined VHDL code
Update : 2025-01-13 Size : 117kb Publisher : DoubleP

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CPU VHDL based design
Update : 2025-01-13 Size : 45kb Publisher : DoubleP

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A part of VHDL design book
Update : 2025-01-13 Size : 4.08mb Publisher : DoubleP

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My summary of the design and analysis of UART, has been applied in practical engineering, and with source code and simulation code, summary of the document, very useful.
Update : 2025-01-13 Size : 227kb Publisher : 何河

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I have written for SRAM chip Verilog read and write procedures, very useful
Update : 2025-01-13 Size : 5kb Publisher : 何河

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I have written for I2C chip Verilog read and write procedures, very useful
Update : 2025-01-13 Size : 2kb Publisher : 何河

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basic files for verilog program in FPGA
Update : 2025-01-13 Size : 1.16mb Publisher : summergirl

i2c master slave VHDL code
Update : 2025-01-13 Size : 4kb Publisher : budavarapu

VHDL/Verilog implementation
Update : 2025-01-13 Size : 96kb Publisher : budavarapu

TRI Ethernet implementation in VHDL
Update : 2025-01-13 Size : 3.04mb Publisher : budavarapu

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FPGA project design, 12864 shows Chinese characters.
Update : 2025-01-13 Size : 72kb Publisher : tws1011

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Digital clock (total) the whole point timekeeping, 8 digital display. VHDL language design....
Update : 2025-01-13 Size : 1.91mb Publisher : tws1011
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