VHDL-FPGA-Verilog List Page 254

VHDL-FPGA-Verilog list

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键盘实验文件_modify Downloaded：0: Read the keyboard data, and display on the digital tube, frequency speed can reach 100M
Update : 2025-01-13 Size : 12kb Publisher : B_button
zhong5 Downloaded：0: Basys2 development board programmer, can dynamically display the date when the minutes and seconds and temperature on the LCD1602 screen, and you can manually set the alarm clock and the upper temperature limit alarm.
Update : 2025-01-13 Size : 1.99mb Publisher : 陈诚
JTAG_Example0_Verilog Downloaded：0: tap_top.v This file is part of the JTAG Test Access Port (TAP) http://www.opencores.org/projects/jtag/ Author(s): Igor Mohor (igorm@opencores.org)
Update : 2025-01-13 Size : 377kb Publisher : ZhouGuofei
ARM JTAG Debug Downloaded：0: OPEN-JTAG Development Group.
Update : 2025-01-13 Size : 452kb Publisher : ZhouGuofei
Lab3 Downloaded：0: Use this code to practice zynq library
Update : 2025-01-13 Size : 6kb Publisher : suni
spi-master Downloaded：1: code for Master side
Update : 2025-01-13 Size : 119kb Publisher : suni
SPI-Master-master Downloaded：0: Use code for Maser SPI
Update : 2025-01-13 Size : 12kb Publisher : suni
2015_2_zynq_labdocs_pdf Downloaded：0: These are bocks for Zynq FPGA
Update : 2025-01-13 Size : 4.3mb Publisher : suni
eda Downloaded：0: Based on VHDL+ FPGA design of the DDS signal has been through mode
Update : 2025-01-13 Size : 196kb Publisher : 丢丢的人生
UART Downloaded：0: UART Verilog source hope useful for all!
Update : 2025-01-13 Size : 1kb Publisher : qcleo
Freq_gen Downloaded：0: XILINX frequency divider 100MHz, 1KHz, 1Hz
Update : 2025-01-13 Size : 991kb Publisher : hush_puppy
vga_pingpong Downloaded：0: Development of VGA display based on FPGA
Update : 2025-01-13 Size : 997kb Publisher : 湾仔

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